Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — IEDM 2023
22 slides from Applied Materials's conference presentation, 2023
Slide 1: The Future of Logic: Gate-All-Around Is Here, Now What?
CLARE, THE FUTURE OF LOGIC Gate-All-Around Is Here, Now What?
Slide 2: Bala Haran, Vice President, Integrated Materials Solutions
Bala Haran Vice President, Integrated Materials Solutions Semiconductor Products Group 2 | Applied Materials External
Slide 3: 2019 Panel Takeaways
2019 Panel Takeaways EUV Is Here, Now What? ▪ AI beginning to shape the technology roadmap ▪ New approaches needed to drive innovation ▪ Requires co-optimization from materials to systems A new playbook for collaborative innovation 3 | Applied Materials External
Slide 4: What’s Changed Since 2019?
What’s Changed Since 2019? IoT +AI 3D Complexity Cloud and edge AI driving 3D accelerating across Complexity increasing new wave of growth and multiple vectors, from across entire process innovation device to system level technology roadmap 4 | Applied Materials External
Slide 5: Panelists
Nick Yu PR Chidambaram Kevin Fischer Dong-Won Kim Geoffrey Yeap Victor Moroz Paul Lindner Google Qualcomm Intel Samsung TSMC Synopsys EV Group Custom Silicon VP of Engineering VP, Interconnect Fellow, Logic VP, Research & Fellow Executive Technologist and Memory Technology Development Technology Dir
Slide 6: Google’s Cloud TPU v4
Google’s Cloud TPU v4 Google’s Cloud TPUv4 enabled: ▪ a nearly 10x leap forward in scaling ML system performance over TPU v3 ▪ boosting energy efficiency ~2-3x compared to contemporary ML DSAs, and ▪ reducing CO2e as much as ~20x over these DSAs in typical on-premise data centers TPU v4 provides exa
Slide 7: LLMs own Moore’s Law?
LLMs own Moore’s Law? Google
Slide 8: LLMs own Moore’s Law?
LLMs own Moore’s Law? Google LANGUAGE MODEL SIZES TO MAR/2023 2023-2024 OPTIMAL LANGUAGE MODELS
Slide 9: LLMs own Moore’s Law?
LLMs own Moore’s Law? https://huggingface.co/blog/large-language-models 9
Slide 10: LLMs own Moore’s Law?
LLMs own Moore’s Law? Google 10 Relative Performance 30 20 10 oo Google’s Cloud TPU v5 [Announced 6th Dec 2023] Training Speed (GPT3-175B Training) 25 20 15 10 Relative perf/$ 05 00 TPU v4 (bf16) ‘TPU vop (116) TPU vop (ints) Relative Perf/$ (GPT3-175B training) TPU v4 (br16) TPU v5e (int8) TPU v5p
Slide 11: Gen AI to Accelerate Innovations in Our Industry
Gen AI to Accelerate Innovations in Our Industry Key System Themes Digging Deeper ▪ GPUs vs DSAs ▪ Die size scaling, intrinsic area scaling ▪ Memory (more HBM, what’s next) » Computation and Power density ▪ Chiplets (what’s next) ▪ New memory - overcome logic-to-memory bottleneck ▪ Interconnect (opt
Slide 12: Digital Switching and Leakage Power Will Limit Industry
Digital Switching and Leakage Power Will Limit Industry Mobile Power Profile Change ▪ Product power reductions 50 slowing for lack of true universal curve gain 40 ▪ Multi-die/Chiplet mostly help 30 with memory access power 20 ▪ DTCO based power gains 10 advertised hard to realize on 0 product Comput
Slide 13: EUV is Here, Now What?
2023 Gate All Around 2019:“The Future of Logic. EUV is Here, Now What?” ▪ The State of Logic is STRONG ▪ Adv. Logic Tech: (5nm mass production in 1H ’20) 1) Mobile AI mobile N3/N4/N5 in mass production 2) High Performance Computing AI data center scale computing ▪ The Future of Logic is BRIGHT 3) Au
Slide 14: System Scaling Innovation
System Scaling Innovation Enabled by TSMC Adv Logic + 3DFabricTM (CoWoS, SoIC, and InFO) Technologies 14
Slide 15: AI Revolution Driven by Semiconductors
AI Revolution Driven by Semiconductors 15
Slide 16: Performance Per Watt: Intel Roadmap
Intel Roadmap: Next Step in 5 Nodes in 4 Years Angstrom era PowerVia and Intel RibbonFET on Intel EUV Intel NEXT Litho Intel 18A 20A and Intel 18A Performance Per Watt Super MIM Intel 20A Capacitor Intel 3 Ribbon ▪ Improved perf. per COAG innovation Intel 4 RibbonFET & increased watt First Intel 7 P
Slide 17: Frontside Power Delivery vs PowerVia
Frontside Power Delivery vs PowerVia Frontside Power Delivery PowerVia Backside Power Delivery Signal wires and power wires compete for Signal wires and power wires are the same resources at every metal layer decoupled and optimized separately Requires aggressive scaling of metal Value Proposition:
Slide 18: MBCFET Learning and Future
MBCFET™ Learning and Future FinFET MBCFETTM and its derivatives Key Messages 14nm 3nm ▪ Learnings from the 3nm MBCFET ramp MBC MBC 3 stack 4 stack N P » Metrology & Inspection » Limited spacing for metal gate ’04 IEDM 1st Gen. ‘05 US » Co-optimization of devices with wide/narrow widths patent 3DSFET
Slide 19: EDA Role in Advanced CMOS Eco-System
EDA Role in Advanced CMOS Eco-System 10000 EDA+DTCO Key Messages 1000 AI-Driven EDA Suite ▪ Collaboration with Foundries & PPA 100 Litho 10 Fabless to Optimize EDA tools for 1 » GAA & CFET (Si, SiGe, stress) 2000 2020 2040 » BS PDN (power, clock, signal) » Chiplets (hybrid bonding, I/O devices) » Li
Slide 20: Wafer Bonding is a Scaling Booster
Wafer Bonding is a Scaling Booster EVG®40NT NanoCleave™ Gemini®FB ▪ Wafer Bonding Bond Overlay Cleaving Hybrid Metrology Bonding » Complements the traditional dimensional scaling EVG®850 Integration and Packaging 3D IC Technologies in 2.5 and 3D Temporary Bonding BONDSCALE® ▪ Wafer-to-Wafer Active L
Slide 21: Panelists
Nick Yu PR Chidambaram Kevin Fischer Dong-Won Kim Geoffrey Yeap Victor Moroz Paul Lindner Google Qualcomm Intel Samsung TSMC Synopsys EV Group Custom Silicon VP of Engineering VP, Interconnect Fellow, Logic VP, Research & Fellow Executive Technologist and Memory Technology Development Technology Dir
Slide 22: | Applied Materials External
| Applied Materials External