Intel Corporation · NASDAQ:INTC
Intel — Investor Day (November 2015)
25 slides from Intel's investor day presentation, Nov 20, 2015
Slide 1: Investor Meeting 2015 Santa Clara
investor meeting 2015 SANTA CLARA
Slide 2: Advancing Moore's Law
Advancing moore’s law Bill Holt Executive Vice President General Manager, Technology and Manufacturing Group
Slide 3: Agenda
Agenda Progress 14nm Update Cost per Transistor Trend Economics of Moore’s Law – What does it take to afford to continue? Competitiveness Forward looking options
Slide 4: 14nm Product Yield Is In Healthy Range
14 nm Product Yield Is In Healthy Range 14nm Broadwell Yield Trend Increasing Yield Investor Meeting 2014 22nm Is Intel’s Highest Yielding Process Ever 22 nm data are shifted to align date of lead product qual
Slide 5: 14nm Yield Is Maturing
14 nm Yield Is Maturing 1H’14 2H‘14 1H’15 2H’15 1H’16 22 nm data are shifted to align date of lead product qual Trending to match 22nm yields Source: Intel
Slide 6: Cost per Transistor Trend
Cost per Transistor Trend 0.1 X 0.01 0.1 + 0.01 $ / mm2 (normalized) mm2 / Transistor (normalized) $ / Transistor (normalized) Source: Intel estimate, based upon available information and subject to change
Slide 7: Agenda
Agenda Progress 14nm Update Cost per Transistor Trend Economics of Moore’s Law – What does it take to afford to continue? Competitiveness Forward looking options
Slide 8: Moore's Law Enables Innovation and Cost Reductions
Moore’s Law Enables Innovation and Cost Reductions 32nm 22nm 14nm 10nm 7nm 5nm Twice the Same circuitry circuitry in the Option to design half the space OR same space = for optimal (cost reduction) (architectural performance/cost innovation) Source: Intel
Slide 9: Advancing Process Technology Lowers Costs
AdvancING Process Technology Lowers Costs Ten Year Model of Manufacturing and Process R & D $302B 2011 Analysis Same ten process years for $104B Process R & D Develop processes new Manufacturing Costs Assumptions are theoretical and not forecasts. Source: Intel
Slide 10: Advancing Process Technology Lowers Costs
AdvancING Process Technology Lowers Costs Ten Year Model of Manufacturing and Process R & D 2015 Update $270B Same ten process years for $116B Process R & D Develop processes new Manufacturing Costs Assumptions are theoretical and not forecasts. Source: Intel
Slide 11: Three Ways To Test the Model
Three Ways To Test the Model: Lower unit demand Higher technology development cost Reduced cost per transistor improvement
Slide 12: Three Ways To Test The Model: Unit Demand Changes
Three Ways To Test THE Model: Unit Demand changes Assumptions are theoretical and not forecasts Source: Intel
Slide 13: Three Ways To Test The Model: R&D Cost Increases
Three Ways To Test THE Model: R&D cost Increases Higher R&D investment growth will NOT limit Moore’s Law Assumptions are theoretical and not forecasts. Source: Intel
Slide 14: Three Ways To Test The Model: CPT Improvement Reduces
Three Ways To Test THE Model: CPT improvement reduces 1.0 Per Cost CPT~0.86 Reduction Normalized Transistor CPT~0.69x 0.1 65nm 45nm 32nm 22nm 14nm 10nm Historical CPT 14nm/10nm Overscaling BE CPT Poorer CPT scaling could challenge economic benefits Assumptions are theoretical and not forecasts Sourc
Slide 15: Agenda
Agenda Progress 14nm Update Cost per Transistor Trend Economics of Moore’s Law – What does it take to afford to continue? Competitiveness Forward looking options
Slide 16: Logic Area Scaling Trend
Logic Area Scaling Trend (Publicly available scaling information)
Slide 17: Estimated Full Chip Scaling
ESTIMATED FULL CHIP SCALING Area scaling estimate includes more of the technology features Sources: TSMC keynote, ARM Tech Con 2012, Oct. 30, 2012, 2014 TSMC Technology Symposium, April 22, 2014, Samsung, Globalfoundries Prep 14nm Process, EE Times 4/17/2014, 2014. 2014 VLSI Technology Symposium abs
Slide 18: Transistor Density From Actual Products
TRANSISTOR DENSITY FROM ACTUAL PRODUCTS Source: Intel Internal analysis Other names and brands may be claimed as the property of others.
Slide 19: Composition Matters
Composition Matters Source: Intel Internal analysis Other names and brands may be claimed as the property of others.
Slide 20: Transistor Density Normalized for Composition
TRANSISTOR DENSITY NORMALIZED FOR COMPOSITION Source: Intel Internal analysis Other names and brands may be claimed as the property of others. Source: Intel internal analysis
Slide 21: Full Chip Scaling Updated With Actual 14/16nm Products
FULL CHIP SCALING UPDATED WITH ACTUAL 14/16NM PRODUCTS Intel 14nm provides significant density advantage Sources: TSMC keynote, ARM Tech Con 2012, Oct. 30, 2012, 2014 TSMC Technology Symposium, April 22, 2014, Samsung, Globalfoundries Prep 14nm Process, EE Times 4/17/2014, 2014. 2014 VLSI Technology
Slide 22: Future Options Being Investigated
Future Options Being Investigated High RF, mm-Wave Voltage HETEROGENEOUS INTEGRATION Sensors/Actuators SELECTIVE Quantum DEPOSITION FUNCTION INTEGRATION SYSTEM DIRECTED SELF-ASSEMBLY Flexible/Stretchable RRAM and STTM Nanowire Tunnel FET III-V III-V Spin-based SCALING Source: Intel
Slide 23: Summary
Summary 14nm yields, availability and product portfolio MATURING Cost per Transistor is difficult, but progress is PROMISING Economics of Moore’s Law for Intel are SOLID Our view of competition is UNCHANGED Innovation and change will be required looking forward but…. The research pipeline is challen
Slide 24: Investor Meeting 2015 Santa Clara
investor meeting 2015 SANTA CLARA
Slide 25: Risk Factors
Risk Factors The statements in this presentation and other commentary that refer to future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “c