Slide 1: New CXL Product Line to Scale Memory Bandwidth and Capacity in Cloud
New CXL Product Line to Scale Memory Bandwidth and Capacity in Cloud July 30, 2024
Slide 2: Forward-looking statements
Forward-looking statements Except for statements of historical fact, this presentation contains forward-looking statements (within the meaning of the federal securities laws) including statements related to future revenue, future earnings, and the success of our product releases that involve risks a
Slide 3: Overview
Overview Company founded FY24 revenue 1995 $5.5B Employees Patents worldwide 6,800+ 10,000+ Global fabless semiconductor supplier -100 © 2024 Marvell. All rights reserved. 3
Slide 4: Data center server market trends
Data center server market trends CPU core growth outpacing memory bandwidth growth Constrained CPU pin-count limiting memory capacity Sustainability and CAPEX driving memory recycling initiatives © 2024 Marvell. All rights reserved. 4
Slide 5: Compute Express Link (CXL) addressing trends
Compute Express Link (CXL) addressing trends Cache Cache HBM dth dth wi HBM wi nd nd DRAM ba ba O, O, , I/ , I/ cy Pr cy ten Pr DRAM ic ten ic e : la e : la ce ce an an rm rm rfo rfo Pe NVMe flash storage Pe NVMe flash storage HDD storage HDD storage Inexpensive, low-access capacity Fast Storage Ine
Slide 6: CXL addresses memory-intensive applications
CXL addresses memory-intensive applications High-bandwidth Maximize memory bandwidth per core: 10GB/s Bandwidth / core ML/AI DLRM inference High-capacity Maximize memory capacity per socket: >3TB In-memory Design database simulation © 2024 Marvell. All rights reserved. Capacity 6
Slide 7: Introducing the Marvell Structera CXL product line
Introducing the Marvell® Structera™ CXL product line Applications Structera™ A Near-memory High memory bandwidth compute accelerators Structera™ X Memory-expansion High memory capacity controllers © 2024 Marvell. All rights reserved. 7
Slide 8: Structera A 2504: CXL 2.0 DDR5 4-channel accelerator
Structera A 2504: CXL 2.0 DDR5 4-channel accelerator § CXL 2.0 / PCIe 5.0 x16 port controller § 200 GB/s memory bandwidth § 4 x DDR5-6400 memory channels § Support for up to two DIMMs per channel § 16 Arm® Neoverse® V2 (Demeter) cores at 3.2 GHz § Inline LZ4 compression / decompression § Inline AES-
Slide 9: Structera A 2504 high-level block diagram
Structera A 2504 high-level block diagram Arm Arm Arm Arm DDR5 Neoverse Neoverse Neoverse Neoverse memory v2 CPU v2 CPU v2 CPU v2 CPU controller Arm Arm Arm Arm DDR5 Neoverse Neoverse Neoverse Neoverse memory v2 CPU v2 CPU v2 CPU v2 CPU controller PCIe 5.0 and Compression Coherent Encryption CXL 2.0
Slide 10: Structera A scales compute and memory bandwidth
Structera A scales compute and memory BW Before After Memory bandwidth Memory bandwidth per CPU core per CPU core Cores Cores Enables new high-performance compute architectures © 2024 Marvell. All rights reserved. 10
Slide 11: Deep learning recommendation model (DLRM) server
Deep learning recommendation model (DLRM) server Midplane Compute Fabric Switch PCIe compute fabric Connector Connector Server host AI accelerator CPU XPU motherboard baseboard NIC / DPU Server has 64 cores with 400 GB/s of DRAM bandwidth and consumes 400W power 6.25 GB/s per CPU core and 1 W per GB
Slide 12: DLRM server example with Structera A CXL accelerator
DLRM server example with Structera A CXL accelerator Midplane Compute Fabric Switch PCIe compute fabric Connector Connector Server host AI accelerator CPU XPU motherboard baseboard NIC / DPU Server has 80 cores with 600 GB/s of DRAM bandwidth and consumes 500W power 7.5 GB/s per CPU core and 0.83W p
Slide 13: DLRM server example with 2 Structera A CXL accelerators
DLRM server example with 2 Structera A CXL accelerators Midplane Compute Fabric Switch PCIe compute fabric Connector Connector Server host AI accelerator motherboard CPU XPU baseboard NIC / DPU Server has 96 cores with 800 GB/s of DRAM bandwidth and consumes 600W power 8.33 GB/s per CPU core and 0.7
Slide 14: Structera X 2404: CXL 2.0 DDR4 4-channel expander
Structera X 2404: CXL 2.0 DDR4 4-channel expander § CXL 2.0 / PCIe 5.0 1x16-port or 2x8-port controller § 100 GB/s memory bandwidth § 4 x DDR4-3200 memory channels § Support for up to three DIMMs per channel § Support for >6TB of DRAM memory capacity § Inline LZ4 compression / decompression § Inline
Slide 15: Structera X 2404 high-level block diagram
Structera X 2404 high-level block diagram DDR4 memory controller DDR4 memory controller PCIe 5.0 and Compression Coherent Encryption CXL 2.0 and cache and 4 DDR4-3200 x16 or 2 x8 controller decompression fabric decryption channels DDR4 CXL 2.0 / PCIe 5.0 memory controller DDR4 memory controller JTAG
Slide 16: Structera X 2404 enables DDR4 memory recycling
Structera X 2404 enables DDR4 memory recycling Host server motherboard CPU CPU CXL memory expansion board Recycle up to 12 DDR4 DIMMs per expander (up to 6TB) Increases server memory capacity with lower CAPEX and reduces e-waste © 2024 Marvell. All rights reserved. 16
Slide 17: Structera X 2504: CXL 2.0 DDR5 4-channel expander
Structera X 2504: CXL 2.0 DDR5 4-channel expander § CXL 2.0 / PCIe 5.0 1x16-port § 200 GB/s memory bandwidth § 4 x DDR5-6400 memory channels § Support for up to two DIMMs per channel § Support for >4TB of DRAM memory capacity § Inline LZ4 compression / decompression § Inline AES-XTS 256-bit encrypti
Slide 18: Structera X 2504 high-level block diagram
Structera X 2504 high-level block diagram DDR5 memory controller DDR5 memory controller PCIe 5.0 and Compression Coherent Encryption CXL 2.0 and cache and 4 DDR5-6400 x16 or 2 x8 controller decompression fabric decryption channels DDR5 CXL 2.0 / PCIe 5.0 memory controller DDR5 memory controller JTAG
Slide 19: Structera X 2504 enables DDR5 memory expansion
Structera X 2504 enables DDR5 memory expansion Host server motherboard CPU CPU CXL memory expansion board Up to 8 DDR5 DIMMs per expander (up to 4TB) Increases server memory capacity with high-capacity DDR5 DIMMs © 2024 Marvell. All rights reserved. 19
Slide 20: Structera product family overview summary
Structera product family overview summary Structera A Structera X Near-memory accelerators Memory-expansion controllers CXL 2.0 / 4 x DDRx Industry-first features PCIe 5.0 memory channels to enable CXL adoption © 2024 Marvell. All rights reserved. 20
Slide 21: Structera industry firsts and key features
Structera Industry firsts This is a sample headline 4 memory channel support Higher memory bandwidth and capacity Inline compression Optimizes DRAM capacity 3 DIMMs per channel (3DPC) Maximizes DRAM capacity 5nm process Lower power consumption Multi-host support Improves memory utilization Arm® Neov
Slide 22: Key takeaways
Key takeaways 1 CXL to address data center server memory bandwidth, capacity and recycling trends 2 New Marvell Structera CXL product line optimized for memory-intensive cloud applications 3 Structera devices are 1st to support 4 memory channels, integrate compression and use 5nm 4 Structera A 2504
Slide 23: Thank You
Thank You
Slide 24: Marvell: Essential technology, done right
ia MARVELL Essential technology, done right™