On Semiconductor Corporation · NASDAQ:ON

On Semiconductor — onsemi — Technical Presentation

60 slides from On Semiconductor's technical presentation

  1. Slide 1: NCP1379 / NCP1380 QR Controller

    NCP1379 / NCP1380 QR Controller Design of a QR Adapter with Improved Efficiency and Low Standby Power

  2. Slide 2: Agenda

    Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/1380 4. Step by Step Design Procedure 5. Performances of a 60-W Adapter Featuring Valley Lockout 2

  3. Slide 3: Agenda

    Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/1380 4. Step by Step Design Procedure 5. Performances of a 60-W Adapter Featuring Valley Lockout 3

  4. Slide 4: What is Quasi-Square Wave Resonance?

    What is Quasi-Square Wave Resonance ?  MOSFET turns on when VDS(t) reaches its minimum value.  Minimizes switching losses  Improves the EMI signature valley MOSFET turns on in first valley MOSFET turns on in second valley 4

  5. Slide 5: Quasi-Resonance Operation

    Quasi-Resonance Operation  In DCM, VDS must drop from (Vin + Vreflect) to Vin  Because of Lp-Clump network  oscillations appear  Oscillation half period: t x  Lp Clump 9 vdrain Vin VDS 400 Lp Cout Rload Vin + Vreflect 1:N Vout 300 Vin v drain in v olts Vin plot1 200 SW Clump VDS 100 0 9 964u 9

  6. Slide 6: A Need to Limit the Switching Frequency

    A Need to Limit the Switching Frequency  In a self-oscillating QR, Fsw increases as the load decreases Higher losses at light load if Fsw is not limited  2 methods to limit Fsw:  Frequency clamp with frequency foldback  Changing valley with valley lockout 6

  7. Slide 7: Frequency Clamp in QR Converters

    Frequency Clamp in QR Converters QR mode Second valley First valley  In light load, frequency increases and hits clamp  Multiple valley jumps  Jumps occur at audible range  Creates signal instability 7

  8. Slide 8: Agenda

    Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/1380 4. Step by Step Design Procedure 5. Performances of a 60-W Adapter Featuring Valley Lockout 8

  9. Slide 9: The Valley Lockout

    The Valley Lockout  As the load decreases, the controller changes valley (1st to 4th valley in NCP1380)  The controller stays locked in a valley until the output power changes significantly.  No valley jumping noise  Natural switching frequency limitation 80000 9 vdrain 70000 SWITCHING FREQUENCY

  10. Slide 10: The Valley Lockout

    The Valley Lockout  FB comparators select the valley and pass the information to a counter.  The hysteresis of FB comparators locks the valley.  2 possible operating set points for a given FB voltage. VFB decreases (POUT decreases) VFB increases (POUT increases) 10

  11. Slide 11: Agenda

    Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/1380 4. Step by Step Design Procedure 5. Performances of a 60-W Adapter Featuring Valley Lockout 11

  12. Slide 12: NCP1379/1380 Features

    NCP1379/1380 Features  Operating modes:  QR current-mode with valley lockout for noise immunity  VCO mode in light load for improved efficiency HV-bulk  Protections Rzcd1 Rbou  Over power protection Rstart ZCD / OPP Ct 1 8 Dovp  Soft-start NCP1380 C/D FB OVP/BO 2 7 CS Vcc  Short circuit prote

  13. Slide 13: QR Mode with Valley Lockout

    QR Mode with Valley Lockout  Operating principle:  Locks the controller into a valley (up to the 4th) according to FB voltage.  Peak current adjusts according to FB voltage to deliver the necessary output power. 9 vdrain Fsw (Pout) for a 60 W adapter 400 VCO mode QR operation 1.40E+05 300 VCO mod

  14. Slide 14: VCO Mode

    VCO Mode 1 idrain 2 vdrain 3.30  Occurs when VFB < 0.8 V (Pout decreasing) or VFB < 1.4 V (Pout increasing) idrain in amperes 2.30  Fixed peak current (17.5%1.30 of Ipk,max), variable frequency set by the FB loop. Plot1 1 300m 2 vdrain Ipk max 1 idrain 2 vdrain -700m i d r a ini n a m p e r e s 3.

  15. Slide 15: Combined ZCD and OPP

    Combined ZCD and OPP  Zero-Crossing Detection (ZCD) and Over Power Protection (OPP) are achieved by reading the Aux. winding voltage  ZCD function used during the off-time of MOSFET (positive voltage).  OPP function used during the on-time of MOSFET (negative voltage) 1 vzcd 2 drv Rzcd 1 43.0 2.5

  16. Slide 16: NCP1380 Versions

    NCP1380 Versions  4 versions of NCP1380: A, B, C and D OTP OVP BO Auto-Recovery Latched Over current protection Over current protection NCP1380 / X X X A NCP1380 / X X X B NCP1380 / X X X C NCP1380 / X X X D OTP: Over Temperature Protection OVP: Over Voltage Protection BO: Brown-Out 16

  17. Slide 17: Short-Circuit Protection

    Short-Circuit Protection  Internal 80-ms timer for short-circuit validation.  Additional CS comparator with reduced LEB to detect winding short-circuit.  VCS(stop) = 1.5 * VILIMIT S Q DRV Q R CS LEB1 + PWMreset Rsense - FB/4 Down Up TIMER Stop controller ZCD/OPP IpFlag OPP Reset V ILIMIT grand re

  18. Slide 18: Short-Circuit Protection (A and C versions)

    Short-Circuit Protection (A and C versions)  A and C versions: the fault is latched.  VCC is pulled down to 7 V and waits for ac removal. S Q DRV Q Vdd R aux Vcc latch VCC management CSstop fault VCCstop CS after LEB1 + PWMreset grand reset FB/4 - SCR delatches Down when + Up TIMER ICC < ICCLATCH

  19. Slide 19: Short Circuit Protection (B and D)

    Short Circuit Protection (B and D)  Auto-recovery short circuit protection: the controller tries to restart  Auto-recovery imposes a low burst in fault mode. Low average input power in fault condition S Q to DRV stage Vdd aux Q Vcc R VCC management fault CS after LEB1 + PWMreset grand VCCstop rese

  20. Slide 20: Fault Pin Combinations

    Fault Pin Combinations  OVP / OTP  OVP / BO  NCP1380 A & B versions  NCP1380 C & D versions, NCP1379 VFault VFault Latch! Latch! OK OK Latch! BO time time  OVP and OTP or OVP and BO combined on one pin.  Less external components needed. 20

  21. Slide 21: Agenda

    Agenda 1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique 3. The NCP1379/1380 4. Step by Step Design Procedure 5. Performances of a 60-W Adapter Featuring Valley Lockout 21

  22. Slide 22: Step by Step Design Procedure

    Step by Step Design Procedure  Calculating the QR transformer  Predicting the switching frequency  Implementing Over Power Compensation  Improving the efficiency at light load with the VCO mode  Choosing the startup resistors  Implementing synchronous rectification 22

  23. Slide 23: Design Example

    Design Example  Power supply specification: Vout = 19 V Pout = 60 W Fsw,min = 45 kHz (at Vin = 100 Vdc) 600 V MOSFET Vin = 85 ~ 265 Vrms Standby power consumption < 100 mW @ 230 Vrms Vout Vbulk T1 . . Gnd 23

  24. Slide 24: Turns Ratio Calculation

    Turns Ratio Calculation  Derate maximum MOSFET BVdss: Vds ,max BVdss k D BVdss kD: derating factor Vds,max 15% derating  For a maximum bulk voltage, select the clamping voltage: Vos Vclamp Vclamp Vds ,max  Vin ,max  Vos Vreflect Vos: diode overshoot Vbulk,max  Deduce turns ratio: N s kc (Vout

  25. Slide 25: How to Choose kc

    How to Choose kc  kc choice dependant of Lleak (leakage inductance of the transformer)  kc value can be chosen to equilibrate MOS conduction losses and clamping resistor losses. 600-V MOSFET PRclamp PMOS,on @ Vin,min Ploss (W) kleak=0.01 kleak=0.008 Ptot  2.5 W kleak=0.005 kc Pout kc PRclamp kle

  26. Slide 26: Primary Peak Current and Inductance

    Primary Peak Current and Inductance  Pout  1 Lpri I pri , peak 2 Fsw DCM 2 Ipri,peak ton toff ton toff tv 0 tv I pri , peak L pri I pri , peak Lpri N ps  Tsw     Lpri Clump Coss contribution Vin ,min Vout  V f alone. Pout  1 N ps  2 Pout Clump Fsw 2 Pout I pri , peak 2      Lpri 

  27. Slide 27: RMS Current

    RMS Current  Calculate maximum duty-cycle at maximum Pout and minimum Vin: I pri , peak Lpri d max  Fsw,min Vin , min  Deduce primary and secondary RMS current value: d max I pri ,rms I pri , peak 3 I pri , peak 1  d max I sec ,rms  N ps 3 Ipri,rms and Isec,rms Losses calculation 27

  28. Slide 28: Design Example

    Design Example  Based on equations from slides 11 to 14: kc (Vout  V f ) 1.3 (19  0.8)  Turns ratio: N ps    N ps 0.25 BVdss k D  Vin ,max  Vos 600 0.85  375  10 2 Pout  1 N ps  2 Pout Clump Fsw  Peak current: I pri , peak         Vin,min Vout  V f   2 60  1 0.25  2

  29. Slide 29: Predicting the Switching Frequency

    Predicting the Switching Frequency  The controller changes valley as the load decreases. => How can we predict the switching frequency evolution as the load varies ?  Depending upon the power increase or decrease, the FB levels at which the controller changes valley are different => valley lockout

  30. Slide 30: Predicting the Switching Frequency

    Predicting the Switching Frequency  Knowing the FB threshold values, we can calculate Fsw evolution and the corresponding Pout. 1 Fsw   VFB t prop   1 N ps    Vin ,dc  Lp     1  2n  L pClump  4 Rsense L p   Vin ,dc Vout  V f  2 1  VFB t prop  Pout  Lp    Vin ,dc  Fs

  31. Slide 31: Predicting the Switching Frequency

    Predicting the Switching Frequency  Calculate by hand (using the previous equations) or use the Mathcad spreadsheet to deduce the maxima of the switching frequency => EMI 83 kHz 93 kHz 90 kHz 95 kHz 3rd 2nd 1st VCO 4 th Fsw (Hz) mode 4th 3rd 2nd 1st VCO Pout decreases mode Pout increases Pout (W) 3

  32. Slide 32: VCO Mode

    VCO Mode  The switching frequency is set by the end of charge of Ct capacitor  The end of charge of Ct capacitor is controlled by the FB loop Vdd Load Rpullup FB Enable VCO mode Vdd 6.5-(10/3)Vfb VCO VFBth ICt - Ct + VCt Controlled by FB loop Ct Ct discharge DRV S Q Q R CS comparator (Timing capac

  33. Slide 33: 4th Valley to VCO Mode Transition

    4th Valley to VCO Mode Transition  Output load slightly decreases: Load VFB 1.4 V 0.8 V VFBth Tsw2 Tsw1 4th valley VCO mode 33

  34. Slide 34: How to Calculate Ct Capacitor?

    How to Calculate Ct Capacitor ?  Switching frequency at the end of the 4th valley operation (VFB = 0.8 V):  0.8 Vin ,max 2   1 N ps  Tsw,4th  VCO  t  Lp     7 Lp COSS  4 Rsense prop Lp       Vin ,max 2 Vout  V f   Tsw gap between 4th valley and VCO mode must not exceed 10 µs

  35. Slide 35: Ct Design Example

    Ct Design Example  Switching frequency at the end of the 4th valley operation :  0.8 265 2   1 0.25  Tsw,4th  VCO   300n  285µ     7 285µ 250 p  4 0.23 285µ   265 2 19  0.8  10.7 µs  Tsw gap between 4th valley and VCO mode must not exceed 10 µs (based on lab experiments): T

  36. Slide 36: OPP: How it Works?

    OPP: How it Works ?  Laux with flyback polarity swings to –NVIN during the on time.  Adjust amount of OPP voltage with (Rzcd+Ropu) // Ropl.  VCS,max = 0.8 V + VOPP  The diode bypass Ropu during the off-time for optimum zero-crossing detection. Rzcd Ropu Peak current CS ZCD/OPP + set point IpFlag

  37. Slide 37: OPP Amount Needed for the Design

    OPP Amount Needed for the Design  Because of the propagation delay, at high line: 0.8 t prop 0.8 600 10  9 I pk ( high )   Vin ,max 2 I pk ( high )   265 2 4.32 A Rsense Lp 0.23 290 10  6  The switching frequency is:  1 N ps  Tsw( high ) I pk ( high ) Lp      L pClump V   in ,m

  38. Slide 38: Amount of OPP Voltage Needed

    Amount of OPP Voltage Needed  Limit the output power to Pout(limit) = 70 W at high line.  What is the peak current Ipk(limit) corresponding to Pout(limit) ? 2  1 N ps  2  1 N ps  Lp Lp     Lp     2  Lp Clump V V  V V V  V P  in ( max ),dc out f   in ( max ),dc out f  out (

  39. Slide 39: Calculating the OPP Resistors

    Calculating the OPP Resistors  The amount of OPP voltage needed to limit Pout to 70 W is : VOPP = 300 mV  Resistor divider law: Rzcd Ropu  Rzcd N p ,auxVIN  VOPP Ropu  ZCD/OPP Ropl VOPP 1 Ropl Ropu  Rzcd 0.18 375  0.3 Aux  224 Ropl 0.3  We choose: Ropl = 1 kΩ and Rzcd = 1 kΩ Ropu 221 Rop

  40. Slide 40: Why is the OPP Non Dissipative?

    Why is the OPP Non Dissipative ?  Input voltage information given by auxiliary winding  In light load: VCO mode => Tsw expands, thus the average current in the resistor bridge decreases 1 ton 1 toff I bridge ,avg  Rzcd  Ropu  Ropl Tsw N p ,auxVIN  Ropu  Ropl Tsw VCC  V f   Previous exampl

  41. Slide 41: Startup Network

    Startup Network Bulk I1 I1 D4 D3 Rstartup Rstartup/3.14 Vcc D1 Vcc D2 D6 D5 CVcc Laux CVcc Laux Classical configuration Improved startup dissipation  The startup resistor can either be connected:  To the bulk capacitor with Rstartup  To the half-wave – for a similar charging current, take Rstartu

  42. Slide 42: Startup Capacitor Calculation

    Startup Capacitor Calculation  CVcc calculated to allow the power supply to close the loop before VCC falls below VCC(off) CVcc   I CC 3A  Qg Fsw treg VCC ( on )  VCC(off) VCC CVcc  2.4m  17n 45000 10m 3.9 µF 17  9 treg tstartup We choose CVcc = 4.7 µF  Needed startup current to charg

  43. Slide 43: Startup Resistor Calculation

    Startup Resistor Calculation  Bulk capacitor connection  Half wave connection  Resistor calculation:  Resistor calculation: Vin ,min 2 Vin ,min 2 Rstartup  I Cvcc  ICC ( start ) Rstartup   I Cvcc  I CC ( start ) 85 2 85 2  Rstartup  2.76 M  Rstartup  880 k  28.5µ  15µ 28.5µ  15µ 

  44. Slide 44: Synchronous Rectification

    Synchronous Rectification  High rms currents in secondary side  increased losses in the output diode.  Replace the diode with a MOSFET featuring a very low RDS(on). Vout + . Cout - . Rload Degraded light load and Increased efficiency Q sync standby Gnd power consumption Vout . Cout . Q sync Gnd 4

  45. Slide 45: Losses in the Sync. Rect. Switch

    Losses in the Sync. Rect. Switch PQsync PON  PQdiode  Body diode conduction losses  Body diode conducts before the MOSFET is turned-on. PQdiode V f I out Fswt delay No switching losses Low if tdelay small tdelay Vout  MOSFET conduction losses . Cout 2 . Rload PON RDS ( on )120 I sec ,rms Q sy

  46. Slide 46: Choosing the Sync. Rect. MOSFET

    Choosing the Sync. Rect. MOSFET  Target around 1 W conduction losses in Sync. Rect. switch to avoid using an heatsink. Vout = 19 V 1W RDSon120  Fsw,min = 45 kHz I sec , RMS 2 Universal mains RDSon110 = 70 mΩ MBR20H150 RDSon110 = 50 mΩ Ploss (W) RDSon110 = 30 mΩ Iout (A) 46

  47. Slide 47: 60 W QR Sync. Rect. Calculations

    60 W QR Sync. Rect. Calculations  Body diode losses: PQdiode V f I out Fswtdelay 0.7 3.2 45000 70n PQdiode 7 mW  MOSFET losses: PON RDS ( on )120 I sec , rms 2 30m 5.82 PON 1W  Total Sync. Rect. switch losses: PQsync 1  0.007 1W  Losses into the MBR20200 diode: 2.6 W Power loss savi

  48. Slide 48: Agenda

    Agenda 1. Quasi-Resonance (QR) Generalities 2. The valley lockout technique 3. The NCP1379/1380 4. Step by step design procedure 5. Performances of a 60-W adapter featuring valley lockout 48

  49. Slide 49: 60-W Demoboard Schematic

    60-W Demoboard Schematic C1 2.2n R4 R11 18k 18k X18 Rx KBU4K 10 Vout R18 L3 + TO-220 1k 2.2u IN . . D2 MBR20H150 - R2 1500k D5 . C5a C5b C7 R1 D4 D1 1N4937 680uF 680uF 100uF Gnd 240k 1N4148 1N4937 35V 35V 25V C18 C14 100n 100u R6 C15 1200k T1 2.2nF Gnd Type = Y1 X1 10 mH DIP8 R5 D6 L1 2A 1N967 R9 27

  50. Slide 50: Startup

    Startup  Startup resistor connected to  Startup resistor connected to the the bulk rail (Rstartup = 2.7 MΩ) half-wave (Rstartup = 910 kΩ)  Tstartup = 2.68 s  Tstartup = 2.1 s VCC VCC Tstartup = 2.68 s Tstartup = 2.1 s 50

  51. Slide 51: Transient Load Step

    Transient Load Step  Load step: 3% to 100% of output load with a slew rate of 1 A / µs  Vin = 230 Vrms The overshoot / undershoot is 1% of the nominal value of Vout 51

  52. Slide 52: Short-Circuit

    Short-Circuit  A short-circuit is made at the board output.  The circuit pulses with a low VCC burst (5%)  The measured averaged input VCC(off) power is: Pin = 412.4 mW for Vin = 230 Vrms VDRV 52

  53. Slide 53: Efficiency

    Efficiency 115 Vrms 230 Vrms Pout (W) Pout (%) Pin (W) Eff. (%) Pout (W) Pout (%) Pin (W) Eff. (%) 60.6 100 68.65 88.3 60.6 100 68.00 89.1 45.5 75 51.29 88.7 45.5 75 51.43 88.4 30.3 50 34.40 88.2 30.3 50 34.78 87.3 15.2 25 17.61 86.4 15.2 25 17.66 86.1 1.0 1.30 76.4 1.0 1.325 75.4 0.7 0.94 74.5 0.7

  54. Slide 54: Improving the No Load Consumption

    Improving the No Load Consumption  At very low output load, the TL431 bias is removed using a special circuit: Vout L3 2.2u . D2 MBR20H150 . C5a C5b C7 680uF 680uF 100uF Gnd 35V 35V 25V C15 2.2nF Gnd Type = Y1 R9 R5 1k 27k TL431 bias suppresion circuit R7 39k C10 47n X5 TL431_G R8 10k Gnd 54

  55. Slide 55: No Load Consumption

    No Load Consumption  Rstartup connected to the bulk rail:  Without TL431 bias: 115 Vrms 230 Vrms Pout = 0 W Pin = 60 mW Pin = 98 mW  With TL431 bias: 115 Vrms 230 Vrms Pout = 0 W Pin = 98 mW Pin = 128 mW 3 MΩ resistor to discharge X2 capacitor included 55

  56. Slide 56: No Load Consumption

    No Load Consumption  Rstartup connected to the half wave:  Without TL431 bias, Rstartup = 1.1 MΩ (Tstartup = 2.6 s @ 85 Vrms) 115 Vrms 230 Vrms Pout = 0 W Pin = 55 mW Pin = 90 mW 3 MΩ resistor to discharge X2 capacitor included 56

  57. Slide 57: Synchronous Rectification Schematic

    Synchronous Rectification Schematic L3 Vout T1 0.5u . C5a C5b C7 IRFS4321 680µF 680µF 100uF Gnd M3 35V 35V 16V C15 2.2nF Gnd R9 R28 TL431 and NCP4302 10 D2 1N4148 bias suppression circuit 1k R5 27k  TL431 and NCP4302 bias removed at light R10 75 X1 DIP4302 R7 39k load. 1 Sync Vcc 8 C10 47n 7 DRV 3

  58. Slide 58: Efficiency and No Load Consumption

    Efficiency and No Load Consumption 115 Vrms 230 Vrms Pout (W) Pout (%) Pin (W) Eff. (%) Pout (W) Pout (%) Pin (W) Eff. (%) 60.5 100 67.18 90.1 60.5 100 66.48 91.0 45.4 75 50.23 90.5 45.4 75 50.38 90.1 30.3 50 33.78 89.8 30.3 50 34.2 88.6 15.2 25 17.39 87.4 15.2 25 17.48 86.8 1.0 1.319 75.7 1.0 1.368

  59. Slide 59: Conclusion

    Conclusion  The valley lockout technique allows to solve the valley jumping problem in QR power supplies.  NCP1380, NCP1379 features: • QR current-mode with valley lockout for noise immunity for high load. • VCO mode in light load for improved efficiency. • OPP, OVP, BO, OTP, soft-start for buildi

  60. Slide 60: NCP1379 vs NCP1380

    NCP1379 vs NCP1380  Differences between the two devices: NCP1380 NCP 1379 (A, B, C, D versions) VCC(on) 12 V 17 V 1.2 mA < 20 µA Startup current (Need an aux. power supply) (Startup resistors) Fault pin OTP / OVP (A&B versions) BO / OVP combinations BO / OVP (C&D versions) Short circuit Auto-recove

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