Texas Instruments Incorporated · NASDAQ:TXN
Texas Instruments — Technical Presentation
26 slides from Texas Instruments's technical presentation
Slide 1: Jacinto 7 processors: Overview of key SoC subsystems and features for automotive applications
Jacinto™ 7 processors: Overview of key SoC subsystems and features for automotive applications
Slide 2: Overview agenda
Overview agenda • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture • Memory architecture & data movement HWA GPU • Safety a
Slide 3: Key features and benefits
Key features and benefits • High-performance, highly-integrated, peripheral-rich High speed interconnect 16nm FF processors enable key automotive applications. Safety MCU Hardware accelerators CPUs • Mature, high-quality 16FF process technology DSPs MPUs MCUs HWA provides full automotive support. HW
Slide 4: Heterogeneous processing cores
Heterogeneous processing cores • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU + - * = MMA Arm Arm Hardware accelerators • Application-specific hardware accelerators C7x DSP Cortex A7x 48k/32K each Cortex A7x 48k/32K each Lock Step 32k/48K L1 A
Slide 5: Heterogeneous processing cores
Heterogeneous processing cores • Microprocessing Unit (MPU): High speed interconnect 16nm FF – Arm® Cortex®-A72 dual SMP up to 2 GHz Safety MCU • Cache coherence with system cache Hardware accelerators + - * = C7x DSP MMA Arm Cortex A7x Arm Cortex A7x 48k/32K each 48k/32K each Lock Step • Microcontr
Slide 6: Application-specific hardware accelerators
Application-specific hardware accelerators • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Audio acceleration + - * = Safety MCU MMA Arm Arm ASRC HD ATL Cortex A7x Cortex A7x • Application-specific hardware accelerators C7x DSP 48k/32K each 48k/32K each L
Slide 7: Application-specific hardware accelerators
Application-specific hardware accelerators • Capture and vision acceleration: High speed interconnect 16nm FF – Vision Pre-Processing Accelerator (VPAC) Audio acceleration + - * = Safety MCU • 7th generation TI imaging processor MMA Arm Arm ASRC HD ATL C7x DSP Cortex A7x Cortex A7x 48k/32K each 48k/
Slide 8: Device management architecture
Device management architecture • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture • Memory architecture and data movement H
Slide 9: Memory architecture and data movement
Memory architecture and data movement • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators HWA DSPs MPUs MCUs • Device management architecture 1MB SRAM • Memory architecture and data
Slide 10: Memory architecture and data movement
Memory architecture and data movement • Optimized 3-level memory system: High speed interconnect 16nm FF – Level 1 and 2 caches on CPUs Safety MCU – Up to 8 Mbyte shared L3 cache with Hardware accelerators coherence provided by Multi-core HWA DSPs MPUs MCUs Shared Memory Controller (MSMC) 1MB SRAM –
Slide 11: Safety and isolation features
Safety and isolation features • Key features and benefits High Speed Interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware Accelerators • Application-specific hardware accelerators Lock Step Arm Arm Cortex R5F Cortex R5F 32K/32K L1 32K/32K L1 HWA DSPs MPUs MCUs 64KB RAM 64KB RAM
Slide 12: Safety and isolation features
Safety and isolation features • Safety MCU: High Speed Interconnect 16nm FF – Targeting ASIL-D systems Safety MCU – Voltage, clock and reset isolated with lock- Hardware Accelerators Lock Step Arm Arm step R5, DMA and full peripheral set Cortex R5F 32K/32K L1 Cortex R5F 32K/32K L1 HWA DSPs MPUs MCUs
Slide 13: Virtualization features
Virtualization features • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture CMMU MMU • Memory architecture and data movement
Slide 14: Virtualization features
Virtualization features • Memory Management Unit (MMU): High speed interconnect 16nm FF – CPU 2-stage MMUs for primary cores Safety MCU • IO-MMU: Hardware accelerators CPUs – System MMU (sMMU): HWA DSPs MPUs MCUs • Standard ARMv3 SMMU 2-stage CMMU HWA MMU system MMU GPU – TI IO-MMU: Power isolation
Slide 15: Security management features
Security management features • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture • Memory architecture and data movement HWA
Slide 16: Security management features
Security management features • Secure boot and runtime security: High speed interconnect 16nm FF – Customer-securable device Safety MCU – Secure execution from flash (on-the-fly Hardware accelerators authentication) CPUs HWA DSPs MPUs MCUs • DMSC (Arm Cortex-M3) security manager HWA • Full endpoint
Slide 17: Power management features
Power management features • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture • Memory architecture and data movement HWA GP
Slide 18: Power management features
Power management features • Voltage domains (AVS, power modes): High speed interconnect 16nm FF – Adaptive voltage scaling for main CPUs Safety MCU – Shut off Main domain during MCU-only Hardware accelerators mode CPUs HWA DSPs MPUs MCUs • Power domains: HWA – Internally-switched domains on major GP
Slide 19: Network connectivity
Network connectivity • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture • Memory architecture and data movement HWA GPU • S
Slide 20: Network connectivity
Network connectivity • Ethernet switch: High speed interconnect 16nm FF – Up to eight 1Gbps ports (SGMII, RGMII, Safety MCU RMII or QSGMII) plus 1 port on Safety MCU Hardware accelerators – Hardware classification and traffic shaping CPUs HWA DSPs MPUs MCUs at full 1Gbps line rate – Reset isolation
Slide 21: Flash and storage
Flash and storage • Heterogeneous processing cores High Speed Interconnect 16nm FF • Application-specific hardware accelerators Safety MCU Hardware Accelerators • Device management architecture CPUs HWA DSPs MPUs MCUs • Memory architecture and data movement • Safety and isolation features HWA GPU •
Slide 22: Flash and storage
Flash and storage • Heterogeneous processing cores High Speed Interconnect 16nm FF • Application-specific hardware accelerators Safety MCU Hardware Accelerators • Device management architecture CPUs HWA DSPs MPUs MCUs • Memory architecture and data movement • Safety and isolation features HWA GPU •
Slide 23: Serial connectivity
Serial connectivity • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture • Memory architecture and data movement HWA GPU • Sa
Slide 24: Serial connectivity
Serial connectivity • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Safety MCU Hardware accelerators • Application-specific hardware accelerators CPUs HWA DSPs MPUs MCUs • Device management architecture • Memory architecture and data movement HWA GPU • Sa
Slide 25: Overview summary
Overview summary • Key features and benefits High speed interconnect 16nm FF • Heterogeneous processing cores Audio acceleration + - * = MMA Arm Arm Safety MCU C7x DSP Cortex A7x Cortex A7x ASRC HD ATL • Application-specific hardware accelerators 48k/32K each 48k/32K each Lock Step Lock Step 32k/48K
Slide 26: For more information
For more information • For more training on Jacinto 7 processors: http://training.ti.com/jacinto7 • Download Processor SDK Automotive for Jacinto 7 processors: http://www.ti.com/tool/PROCESSOR-SDK-DRA8X-TDA4X • Order TDA4VM Jacinto Automotive processors for ADAS & autonomous vehicles: http://www.ti.