Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Investor Day (November 2008)
36 slides from Asml Holding Nv's investor day presentation, Nov 10, 2008
Slide 1: Innovation outside the box
Innovation outside the box Lucas van Grinsven Corporate Communications Director 15 October 2008
Slide 2: Agenda for the day
Agenda for the day Morning (0945-1130 hours) Innovation outside the box: new technology unveiled Location: ASML Global Headquarters Afternoon (1200-1600 hours) Break out sessions Location: Koningshof hotel in Veldhoven
Slide 3: Innovation outside the box
Innovation outside the box Jos Benschop Vice President Research 15 October 2008
Slide 4: Launching the new TWINSCAN NXT platform
Launching the new TWINSCAN NXT platform 1. Moore's Law in action 2. Immersion taken to its maximum limit 3. Double Patterning: Three challenges to continue Moore's Law 4. Innovations to continue Moore's Law 5. A look inside the ASML cleanroom
Slide 5: From silicon to smart electronics
$256 B Semiconductor Chips $1,550 B Electronic Applications $8.6 B Semiconductor Litho market Source: VLSI, SIA, Gartner From silicon to smart electronics
Slide 6: Moore's Law: the industry is sustained by the need for cheaper, smaller ICs
Moore's Law: The industry is sustained by the need to make cheaper, smaller ICs that do more
Slide 7: Lithography is at the heart of chip manufacturing
Lithography is at the heart of chip manufacturing
Slide 8: Networked innovation
Networked innovation 90 percent of cost of ASML litho machine is outsourced ASML supplies litho machines to 18 of the top 20 chipmakers: Samsung, Intel, Hynix, Micron, Toshiba, TSMC, Nanya, Powerchip, Infineon, ProMos, AMD, SanDisk, Elpida, Sony, UMC, ST, Fujitsu, IBM Chartered, TI Other equipment s
Slide 9: Hooke's microscope 1665 to ASML Immersion 2004
Robert Hooke Hooke's microscope 1665 Jan Mulkens ASML Immersion 2004
Slide 10: Fluid thinking: the liquid lens scanner
Fluid thinking: the liquid lens scanner Water improves resolution and process latitude Lens Water Lens Air Air
Slide 11: The immersion pool becomes an ocean
The immersion pool becomes an ocean * Source: Stepper market forecast, worldwide, Q208, Gartner Inc. Cumulative number of processed wafers in millions Source: ASML >120 immersion systems have now been shipped to customers worldwide in 2008 by ASML nearly 28 million wafers have now been processed on
Slide 12: XT:1950i - immersion taken to the max
Improved overlay performance to 3.5 nm Productivity up 15 percent to 148 wph (300 mm) 10 percent better resolution Better water quality controls Slide 23 | XT:1950i - immersion taken to the max 25 percent improvement. But what is next?
Slide 13: Chip makers want shrink to continue
'02 '03 '04 '05 '06 '07 '08 '09 '10 '11 '12 '13 '14 Year of production start* Resolution, "Shrink" (nm) 100 80 60 40 Logic NAND Flash DRAM 30 20 50 *Process development 1.5 ~ 2 years in advance (updated 12/07) 200 Chip makers want shrink to continue (based on the average of multiple customers' input
Slide 14: The shrink dilemma solved: Double Patterning
Single Patterning k1 Limit ~ 0.26 Resolution, Half Pitch [nm] 65 60 55 50 45 40 35 30 25 20 Double Patterning XT:19X0i, NA = 1.35 Single Patterning XT:19X0i, NA = 1.35 The shrink dilemma solved: Double Patterning Shrink to 22 nanometers with existing technology!
Slide 15: Challenge 1: Litho DPT requires significant improvement of overlay
0 2 4 6 8 10 12 14 10 100 But: making two exposures is twice as hard Challenge 1: Litho DPT requires significant improvement of overlay Overlay [nm] 20 30 40 50 60 80 Half pitch [nm] Single exposure: overlay tolerance is 20% of CD EUV (single exposure) ArF 193 nm (single exposure) ArF 193 nm Immersi
Slide 16: Challenge 2: DPT drives need for improvement in CDU
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 100 Single-exp. CD Uniformity (CDU) Litho DPT CDU But: making two exposures is twice as hard Challenge 2: DPT drives need for significant improvement in CDU CD uniformity [nm] 20 30 40 50 60 80 Half pitch [nm] Single exposure: overlay tolerance is 7% of CD EUV
Slide 17: Challenge 3: two exposures means more process steps
26 process steps ( 2 litho steps) 14 steps ( 1 litho step) Cost, complexity and cycle time *Wafer does not leave the exposure system between the two exposures But: making two exposures is twice as hard Challenge 3: two exposures means more process steps Single exposure *Wafer leaves litho cell for e
Slide 18: Three focus areas for lithography
Three focus areas for lithography PLACEMENT = Overlay Value for chipmakers: higher yield | shrink enabler (e.g. DPT) PATTERN FIDELITY = CDU (Critical Dimension Uniformity) Value for chipmakers: higher yield | shrink enabler AFFORDABILITY = Productivity Value for chipmakers: higher throughput = highe
Slide 19: Three focus areas for lithography
Three focus areas for lithography PLACEMENT = Overlay Value for chipmakers: higher yield | shrink enabler (e.g. DPT) PATTERN FIDELITY = CDU (Critical Dimension Uniformity) Value for chipmakers: higher yield | shrink enabler AFFORDABILITY = Productivity Value for chipmakers: higher throughput = highe
Slide 20: What does overlay mean?
What does overlay mean? Overlay down to 2 nanometers 1 nm = 4 silicon atoms
Slide 21: Addressing challenge 1: Overlay
Addressing challenge 1: Overlay How to position lines with 2 nm precision (8 Si atoms) Measurement system TWINSCAN XT
Slide 22: Setting 'impossible' targets in 2005: Overlay
Setting 'impossible' targets in 2005: Overlay 2005 2006 2007 2008 Overlay ( nm) ASML natural progression trend line 2 4 6 Overlay target DPT 2 nm Overlay roadmap SE 4 nm 2004 2009 8
Slide 23: Wafer stage metrology impact on overlay
Wafer stage metrology impact on overlay Inter- ferometer 300 mm stage Current stage metrology X-coordinate Y- coordinate Overlay [nm, 99.7%] Overlay: < 2 nm Wafer [#] (prototype) 0 2 4 6 8 10 1 2 3 4 5 6 7 8 9 10 11 Overlay: < 4 nm System [#] (ArF 0.93NA) 0 2 4 6 8 10 1 2 3 4 5 6 7 8 9 10 11 Overlay
Slide 24: Three focus areas for lithography
Three focus areas for lithography PLACEMENT = Overlay Value for chipmakers: higher yield | shrink enabler (e.g. DPT) PATTERN FIDELITY = CDU (Critical Dimension Uniformity) Value for chipmakers: higher yield | shrink enabler AFFORDABILITY = Productivity Value for chipmakers: higher throughput = highe
Slide 25: The expanding role of Computational Lithography
Scanner models Scanner knobs Pattern definition Process control The expanding role of Computational Lithography Helping to improve yield Enlarging the process window for a given IC Keeping the process centered in the process window
Slide 26: Litho exploration - Source Mask Optimization
Litho exploration - Source Mask Optimization Allowing user to balance complexity By combining source expertise from ASML and mask expertise from Brion the customer receives a larger process window with better CD Uniformity Source Source Mask 100 nm Mask Overlapping PW DOF @ 10% EL CD Uniformity 150
Slide 27: Process control requires matched scanners
Process control requires matched scanners Higher productivity with consistent yield Mix of machines Create model of full chip differences between scanners Solution: Measure differences between a few areas in chip per scanner Same imaging better yield Mask (Brion's OPC) Brion software plus ASML know-
Slide 28: Three focus areas for lithography
Three focus areas for lithography PLACEMENT = Overlay Value for chipmakers: higher yield | shrink enabler (e.g. DPT) PATTERN FIDELITY = CDU (Critical Dimension Uniformity) Value for chipmakers: higher yield | shrink enabler PERFORMANCE = Productivity Value for chipmakers: higher throughput = higher
Slide 29: Setting 'impossible' targets: Productivity
Setting 'impossible' targets: Productivity FROM 100 wph = 1 wafer every 36 sec TO 250 wph = 1 wafer every 15 sec
Slide 30: Advanced materials and compact design reduce total weight
Advanced materials and compact design results in total weight reduction of 66% ? Faster acceleration
Slide 31: Acceleration: a comparison
m/sec2 0 10 20 40 70 30 50 60 80 90 100 110 120 130 140 150 Acceleration: a comparison... A stone drops at 9.8 m/sec2 A dragster accelerates at 33 m/sec2 A jet fighter in a catapult at 44 m/sec2 Today TWINSCAN reticle stage accelerates at 88 m/sec2 An attack missile at 50 to 120 m/sec2 The future ve
Slide 32: The new TWINSCAN NXT platform
The new TWINSCAN NXT platform
Slide 33: Three focus areas for lithography
Three focus areas for lithography PLACEMENT = Overlay Value for chipmakers: higher yield | shrink enabler (e.g. DPT) PATTERN FIDELITY = CDU (Critical Dimension Uniformity) Value for chipmakers: higher yield | shrink enabler AFFORDABILITY = Productivity Value for chipmakers: higher throughput = highe
Slide 34: New NXT Platform for Lithography
New NXT Platform for Lithography Holistic litho optimization Requires a combination of Computational and Wafer lithography Mask definition Scanner-to-pattern tuning Metrology Illumination setting Device pattern Printed wafers Measuring CD & Overlay Computational Litho Wafer Litho Mask making Scanner
Slide 35: Dedicated to immersion and Double Patterning
Dedicated to immersion and Double Patterning New facility for lean and clean system manufacturing New ASML immersion production facility
Slide 36: Slide 36