Press release
Teradyne Awarded 2025 TSMC Open Innovation Platform® (OIP) Partner of the Year for TSMC 3DFabric® Testing
NORTH READING, Mass.--(BUSINESS WIRE)-- Teradyne, Inc. (NASDAQ: TER), a leading provider of automated test equipment and advanced robotics, is proud to
About this update from Teradyne, Inc.
[{"type":"text","content":" NORTH READING, Mass.--(BUSINESS WIRE)--\nTeradyne, Inc. (NASDAQ: TER), a leading provider of automated test equipment and advanced robotics, is proud to announce it has been recognized as the 2025 TSMC Open Innovation Platform® (OIP) Partner of the Year for TSMC 3DFabric® Testing. This recognition reflects the strong collaboration between Teradyne, TSMC and the larger OIP ecosystem.\n\n\nThrough the TSMC OIP 3DFabric Alliance, Teradyne worked closely with TSMC, the world’s leading semiconductor foundry, to pioneer multi-die test methodologies for chiplets and TSMC CoWoS® advanced packaging technology. These efforts have significantly improved silicon bring-up efficiency and elevated test quality – marking a key milestone in our industry’s transition to chiplet-based architectures.\n\n\n“At Teradyne, we strongly believe in the open and collaborative ecosystem approach of TSMC’s Open Innovation Platform and look forward to continuing our partnership to drive innovation and deliver exceptional value to our customers,” said Shannon Poulin, President, Semiconductor Test Group at Teradyne. “Teradyne’s strategic investments in UCIe, GPIO, and streaming scan test solutions enable scalable, high-quality testing across die-to-die interfaces. For our customers, this means faster time to revenue for the complex 3D ICs used in demanding AI and cloud datacenter applications.”\n\n\nTeradyne’s comprehensive portfolio of semiconductor and electronics test equipment supports today’s demanding devices and emerging chip architectures across all test insertions, while this innovation enables high-speed scan testing over UCIe die-to-die interfaces at wafer sort or chip probing. Enhancing high-speed test coverage for UCIe interfaces reduces defect escapes, improves the overall cost of quality, and enables faster time-to-market for these complex 3D semiconductors used in AI and cloud datacenter applications.\n\n\n“We congratulate Teradyne for their contributions to the OIP ecosystem, driving innovations that improve silicon bring-up and test quality,” said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. “Our long-standing partnership and collaborative efforts with OIP ecosystem partners like Teradyne enable our customers to accelerate AI proliferation through innovations in high performance, energy-efficient compute, ...