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Taiyo Holdings Launches Next-generation Semiconductor-packaging Material "FPIM (TM) Series," Its First Successful Formation of 3-layer RDL with CD 1.6 Micrometers on 12-inch Wafer
On November 13, 2025, Taiyo Holdings Co., Ltd. (Securities Code: 4626; hereinafter referred to as "Taiyo Holdings"), based in Tokyo, presented a paper, co-authored with imec, one of the world's largest semiconductor research institutions, at the 14th IEEE CPMT Symposium Japan (ICSJ2025), focusing on the "FPIM (TM) Series" (hereinafter referred to as "this material"), a negative-type photosensitive insulating material for fine-pitch RDLs (*1) designed for the damascene process, developed as a nex
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[{"type":"text","content":"- Paper Presented at 14th IEEE CPMT Symposium Japan (ICSJ 2025) -","length":65,"tagName":"p"},{"type":"text","content":"TOKYO, Nov. 13, 2025 /PRNewswire/ -- On November 13, 2025, Taiyo Holdings Co., Ltd. (Securities Code: 4626; hereinafter referred to as "Taiyo Holdings"), based in Tokyo, presented a paper, co-authored with imec, one of the world's largest semiconductor research institutions, at the 14th IEEE CPMT Symposium Japan (ICSJ2025), focusing on the "FPIM (TM) Series" (hereinafter referred to as "this material"), a negative-type photosensitive insulating material for fine-pitch RDLs (*1) designed for the damascene process, developed as a next-generation semiconductor-packaging material.","length":632,"tagName":"p"},{"type":"text","content":"The RDL is an important technology in the most advanced structures of semiconductor packaging for more efficient electrical connections, and it is currently manufactured mainly by the semi-additive process (SAP) (*2). The damascene process (*3), imec suggests, will become essential for forming interconnections with line spacing of 1.6 micrometers or less in the future, as finer wiring is pursued. In response, Taiyo Holdings has been developing this material as a next-generation fine-pitch RDL material for the damascene process and has been conducting joint research with imec since October 2022. In this study, a three-layer RDL structure was formed on a 12-inch wafer using this material, and evaluations were carried out. Each wiring pitch achieved the target dimensions as follows: CD (*4) 1.6 micrometers for the RDL1 layer on the wafer, CD 2.0 micrometers (with a via center-to-center pitch of CD 4.0 micrometers) for the via layer, and CD 1.6 micrometers for the RDL2 layer. These values are extremely close to the resolution limit of the low NA stepper (*5) used in this study. In addition, the evaluation results of the electrical characteristics, specifically, leakage current and resistance, of the RDL1 layer with CD 1.6 micrometers were favorable. As an outcome of this joint research with imec, it was confirmed that this material possesses excellent electrical properties, high resolution, and quality suitable for adaptation to the CMP process (*6).","length":1515,"tagName":"p"},{"type":"text","...