Business
Synopsys Unveils RTL Architect To Accelerate Design Closure
Unique RTL Tuning Environment Reduces Physical Design Iterations MOUNTAIN VIEW, Calif., March 16, 2020 /PRNewswire/ -- Highlights: The RTL Architect product
About this update from Synopsys, Inc.
[{"type":"text","content":"Unique RTL Tuning Environment Reduces Physical Design Iterations\n\n\nMOUNTAIN VIEW, Calif., March 16, 2020 /PRNewswire/ --\nHighlights:\nThe RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff The unified Fusion data model delivers unprecedented capacity and scalability for enabling full-chip hierarchical RTL design flows The new product leverages Synopsys' world-class implementation and golden signoff solutions to deliver results that correlate-by-construction Synopsys and Arm are collaborating on RTL Architect to accelerate the development of next-generation coresSynopsys, Inc. (Nasdaq: SNPS) today announced the immediate availability of RTL Architect™, an innovative product that signifies a shift-left for RTL design closure. Synopsys RTL Architect is the industry's first physically aware RTL design system, which reduces the SoC implementation cycle in half and delivers superior quality-of-results (QoR).\nRTL teams are increasingly faced with the challenges of rapidly exploring domain-specific RTL architectures to achieve significant power, performance and area (PPA) gains to meet the requirements of new market verticals like artificial intelligence and automotive applications. Existing point tool solutions for estimating RTL quality are severely limited due to poor accuracy to downstream implementation. These early design cycle inaccuracies cause downstream implementation tools to compensate, often having to go back and make RTL changes to meet the PPA goals. RTL Architect addresses these challenges utilizing a rapid multi-objective prediction engine derived from the Synopsys Fusion Design Platform implementation environment to predict PPA of downstream implementation accurately. RTL Architect enables RTL designers to pinpoint bottlenecks in their source code to improve RTL quality.\n\"Renesas is designing complex state-of-the-art automotive system on chips (SoCs), which require architecture tuning to drive the highest QoR to differentiate ourselves in our target markets,\" said Hideyuki Okabe, Director, Digital Design Technology Department, Shared R&D EDA Division, Renesas Electronics Corporation. \"Synopsys' RTL Architect will enable us to quickly explore and validate various archi...