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Synopsys' Silicon-Proven DesignWare DDR IP for High-Performance Cloud Computing Networking Chips Selected by NVIDIA
DesignWare DDR IP Delivers High Performance Memory Interface for Compute-Intensive Artificial Intelligence Applications in Multiple Silicon Processes
About this update from Synopsys, Inc.
[{"type":"text","content":"DesignWare DDR IP Delivers High Performance Memory Interface for Compute-Intensive Artificial Intelligence Applications in Multiple Silicon Processes Including 7-nm\n\n\nMOUNTAIN VIEW, Calif., May 28, 2020 /PRNewswire/ --\nHighlights:\nSynopsys' high-quality DesignWare DDR PHY IP provides NVIDIA unmatched performance, latency, and power efficiency DDR PHY supporting multiple DIMMs per channel for DDR5/4 addresses NVIDIA's networking data rate and memory capacity requirements Field-upgradable firmware-based training enables a more robust and reliable channel and facilitates algorithm updates to reduce risk of adopting new memory protocols Synopsys, Inc. (Nasdaq: SNPS) today announced that its silicon-proven DesignWare® DDR5/4 PHY IP will be used by Mellanox, NVIDIA's networking business unit, to address evolving memory requirements in its InfiniBand networking chips targeting high-performance computing and artificial intelligence (AI) applications. The high-quality DesignWare DDR5/4 IP with up to an 80-bit data path and support for multiple DIMMs per channel addresses essential data rate and memory capacity requirements as NVIDIA expands its efforts in high performance and cloud computing. DesignWare DDR5/4 PHY IP, a part of Synopsys' broad memory interface IP portfolio consisting of controllers, PHYs and verification IP for a wide range of processes, supports all the required features to help Mellanox integrate the IP into their ASICs and SoCs with less risk.\nSynopsys' DesignWare DDR5/4 PHY IP offers firmware-based training, which is field upgradable without requiring changes to the hardware, to help customers reduce their risk of adopting new protocols. Firmware-based training also facilitates the use of complex training patterns, enabling highest margin and channel reliability at the system level. For power-efficiency, Synopsys' DDR5/4 PHY IP provides several low-power states with short exit latencies and multiple pre-trained states for dynamic frequency change capability.\n\"High-performance ASICs and SoCs for data-intensive networking and artificial intelligence applications require high-bandwidth off-chip memory technologies that efficiently minimize performance bottlenecks,\" said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. \"The DesignWare DDR5/4 PHY IP, operating at maximum data rate...