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Synopsys Digital and Custom Design Platforms Achieve Certification for TSMC N3 Process
The Platforms Optimize PPA for Next-Generation HPC, Mobile, 5G and AI Designs MOUNTAIN VIEW, Calif., Oct. 20, 2021 /PRNewswire/ -- Highlights: Synopsys
About this update from Synopsys, Inc.
[{"type":"text","content":"The Platforms Optimize PPA for Next-Generation HPC, Mobile, 5G and AI Designs\n\n\nMOUNTAIN VIEW, Calif., Oct. 20, 2021 /PRNewswire/ --\nHighlights:\nSynopsys platforms deliver enhanced features to support new requirements for TSMC N3 and N4 processes The Synopsys Fusion Design Platform facilitates faster timing closure and full-flow correlation from synthesis through timing and physical signoff The Synopsys Custom Design Platform delivers improved productivity In a continuing effort to optimize power, performance and area (PPA) for next-generation system-on-chips (SoCs), Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified the Synopsys digital and custom design platforms for TSMC's 3nm technology. The certification with rigorous validation, based on TSMC's latest version of the design rule manual (DRM) and process design kits (PDKs), is the result of a multi-year collaboration between the two companies. In addition to this certification, Synopsys' digital and custom design platforms have also been certified for TSMC's N4 process.\n\"We're pleased to see the results of our multi-year collaboration with Synopsys and the certification of their design platform solutions on TSMC's most advanced processes that deliver optimized PPA,\" said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. \"Through our strategic collaboration, we are enabling our customers to achieve next-generation HPC, mobile, 5G and AI designs and quickly launch their product innovations to the market.\"\nThe digital design flow, anchored by the tightly integrated Synopsys Fusion Design Platform™, features new technologies to ensure faster timing closure, full-flow correlation from synthesis to place-and-route to timing, as well as physical signoff. The platform has been enhanced to deliver improved synthesis and global placer engines that optimize library cell selection and placement results. To support TSMC's ultra-low-voltage design closure, the Synopsys optimization engine has been improved to use new footprint optimization algorithms. These new technologies, which result from the strategic partnership between the companies, will help provide a PPA boost for designs on TSMC's N3 process.\nThe Custom Compiler™ design and layout solution, part of the Synopsys Custom Design Platform, delivers improved productivity ...