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Synopsys Demonstrates Industry's First PCI Express 5.0 IP Interoperability with Intel's Future Xeon Scalable Processor
Successful Interoperability Enables Low-Risk Integration and Broad Adoption of the PCIe 5.0 Interface in High-Performance Computing SoCs MOUNTAIN VIEW,
About this update from Synopsys, Inc.
[{"type":"text","content":"Successful Interoperability Enables Low-Risk Integration and Broad Adoption of the PCIe 5.0 Interface in High-Performance Computing SoCs\n\n\nMOUNTAIN VIEW, Calif., Oct. 13, 2020 /PRNewswire/ --\nHighlights:\nInteroperability establishes end-to-end 32GT/s PCIe 5.0 link between DesignWare IP for PCI Express 5.0 Complete Solution and future Intel Xeon Scalable processors The DesignWare IP for PCI Express 5.0 delivers industry's lowest latency and highest throughput with optimized power consumption for short and long channels Future Intel Xeon Scalable processors deliver enhanced performance, throughput, and CPU frequencies for AI-infused, analytics, storage & networking workloadsSynopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with Intel to achieve successful system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids). The full-system interoperability, a key milestone in Synopsys and Intel's ongoing collaboration, enables the ecosystem to confidently use the companies' proven technologies to accelerate development of their PCIe 5.0-based products in high-performance computing and AI applications. The DesignWare IP for PCI Express 5.0 has been licensed over a hundred times by customers across all key market segments, delivering the lowest latency and highest throughput IP compared to other solutions in the industry. \n\"Synopsys continues to collaborate with industry leaders like Intel to deliver high-quality IP that help designers address the bandwidth, power, area, and latency demands for the new era of high-performance computing systems,\" said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. \"Achieving successful interoperability between Synopsys' DesignWare IP for PCIe 5.0 and Intel Xeon Scalable processors validates that the IP functions as intended with Intel's industry-standard PCIe 5.0 products, accelerating the path to first-silicon success with less risk.\" \n\"The growth of high-performance computing applications converged with AI workloads requires innovative data connectivity and processing technologies that deliver low latency and fast speeds,\" said Jim Pappas, Director of Technology Initiatives at Intel. \"We are pleased to collaborate with Synopsys, a lead...