Press release
Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation
AI-Driven EDA and Broad IP Solutions Enable Differentiated Designs on TSMC Advanced Processes and SoIC Technologies Key Highlights Certified digital and
About this update from Synopsys, Inc.
[{"type":"text","content":"AI-Driven EDA and Broad IP Solutions Enable Differentiated Designs on TSMC Advanced Processes and SoIC Technologies\nKey Highlights \nCertified digital and analog flows on the TSMC N2P and A16™ processes using TSMC NanoFlex™ architecture boost performance and speed analog design migration3DIC Compiler platform and 3D-enabled IP enable multiple customer tape outs using advanced 3D stacking and CoWoS packaging technologiesAI-optimized photonic flow for TSMC Compact Universal Photonic Engine (TSMC-COUPE™) technology enhances system design performance and addresses multi-wavelength and thermal requirementsIndustry's broadest IP portfolio, on TSMC N2/N2P, optimized for low power, speeds path to silicon success and reduces integration riskSUNNYVALE, Calif., Sept. 24, 2025 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) announced today its ongoing close collaboration with TSMC to deliver multi-die solutions, encompassing advanced EDA and IP products, that support TSMC's leading-edge processes and packaging technologies, driving innovation in AI chip and multi-die design. The 3DIC Compiler exploration-to-signoff platform and IP, tuned for 3D packaging, along with the company's partnership with TSMC on design enablement has resulted in multiple customer tape-outs.\n\n \n \n \n \n \n \n\n \nBuilding on Synopsys' continued collaboration with TSMC is the availability of certified digital and analog flows, along with the enabled Synopsys.ai™ on TSMC's N2P and A16™ processes using TSMC NanoFlex™ architecture. In addition, Synopsys provides robust automotive IP solutions for TSMC N5A and N3A processes and best-in-class Interface and Foundation IP solutions, delivering highest level of safety, security and reliability while enabling maximum performance with the lowest power for advanced chips. \n\"Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape outs on the industry's most advanced packaging and process technologies,\" said Michael Buehler-Garcia, Senior Vice President at Synopsys. \"With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC's advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market.\"\n\"TSMC...