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Synopsys Announces Next-Generation VC SpyGlass RTL Static Signoff Platform
Delivers 3X Higher Performance, Multi-Billion Gate Capacity, and 10X Lower Noise MOUNTAIN VIEW, Calif., Feb. 27, 2020 /PRNewswire/ -- Highlights: Uses trusted
About this update from Synopsys, Inc.
[{"type":"text","content":"Delivers 3X Higher Performance, Multi-Billion Gate Capacity, and 10X Lower Noise\n\n\nMOUNTAIN VIEW, Calif., Feb. 27, 2020 /PRNewswire/ --\nHighlights:\nUses trusted industry-standard SpyGlass engines for signoff confidence 10X reduction in noise leveraging machine learning technology Delivers 3X performance with half the memory for lower server cost Unified debug with Verdi provides visibility across abstraction levels Synopsys Design Compiler and PrimeTime compatibility accelerates signoffSynopsys, Inc. (Nasdaq: SNPS), today announced general availability of the VC SpyGlass™ RTL Static Signoff platform, part of the Synopsys Verification Continuum™ platform, which builds on the proven SpyGlass® technology. The VC SpyGlass platform with multi-core support increases performance by 3X with half the memory footprint. The next-generation platform is enhanced with machine learning technology to reduce noise by 10X with no loss in quality of results using trusted industry-standard SpyGlass engines. \n\"The noise reduction technology in VC SpyGlass enabled us to focus on debugging real issues and discover clock domain crossing issues previously not found,\" said Duen-Min Wang, SoC Engineering Director at SK Hynix. \"In addition, the consistent design behavior between VC SpyGlass and Synopsys Design Compiler reduced our design setup to a single day, with more flexible debug and custom constraints settings.\" \nIncreasing SoC complexity demands verifying correct construction of RTL, clock domain crossing (CDC), and reset domain crossing (RDC) early in the RTL phase of development. Synopsys VC SpyGlass integrates advanced algorithms and analysis techniques that provides designers detailed information and insights about their design much earlier in the RTL phase. It provides a tightly integrated solution for formal-enabled linting to reduce noise and comprehensive CDC and RDC analysis to catch logic issues added during implementation. VC SpyGlass is also natively integrated with Synopsys' Verdi® automated debug system to accelerate root cause analysis for bugs. In addition, the VC SpyGlass platform uses design behavior and Tcl flow consistent with Synopsys' Design Compiler® and PrimeTime® tools to significantly reduce setup time between implementation and verification flows. \n\"Insufficient or incorrect constraints are the primary reason ...