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Synopsys Announces Industry's First CXL 2.0 VIP Solution for Breakthrough SoC Performance
Native System Verilog VIP Features Built-in Coverage, Verification Planning, and Memory-Aware Debug and Performance Analysis MOUNTAIN VIEW, Calif., Nov. 10,
About this update from Synopsys, Inc.
[{"type":"text","content":"Native System Verilog VIP Features Built-in Coverage, Verification Planning, and Memory-Aware Debug and Performance Analysis\n\n\nMOUNTAIN VIEW, Calif., Nov. 10, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's first Verification IP (VIP) for Compute Express Link™ (CXL™) 2.0 designed for breakthrough performance in data-intensive system-on-chips (SoCs). CXL is the next-generation open standard interconnect that enables an ecosystem for high-speed communication between the CPU and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions, as well as memory expansion devices. The technology is built upon the well-established PCI Express® infrastructure, leveraging the PCI Express 5.0 physical and electrical interface. \nSynopsys VIP for CXL uses next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments and speeds up simulation performance allowing users to run greater number of tests and accelerate time to first test. VIP for CXL is natively integrated with Synopsys Verdi® Protocol and Performance Analyzer and includes built-in coverage and verification plans for faster verification closure. In addition, Synopsys' silicon-proven DesignWare® CXL IP delivers a x16 link for maximum bandwidth with low latency, supporting all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.\n\"Synopsys' cache coherency verification IP portfolio, including CXL 2.0, CXL 1.1 and CCIX, enables support of emerging applications with massive data throughput requirements,\" said Vikas Gautam, Vice President of R&D for the Synopsys Verification Group. \"Our growing portfolio of industry-first verification IP and close collaborations with standards organizations and memory vendors enable designers to adopt and integrate the latest interconnect technologies rapidly.\"\n\"The advancement of CXL as an open standard interconnect technology to accelerate next generation data center performance is our singular focus,\" said Jim Pappas, Chairman at CXL Consortium. \"We appreciate Synopsys' support of CXL Consortium to help advance the adoption of CXL technology.\" \n\"Bringing to market the next major interconnect advance...