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Synopsys and TSMC Drive Chip Innovation with Development of Broadest IP Portfolio on TSMC N4P Process
DesignWare Interface and Foundation IP Deliver Optimized Power and Performance for High-Performance Computing and Mobile SoCs MOUNTAIN VIEW, Calif., Oct. 27,
About this update from Synopsys, Inc.
[{"type":"text","content":"DesignWare Interface and Foundation IP Deliver Optimized Power and Performance for High-Performance Computing and Mobile SoCs\n\n\nMOUNTAIN VIEW, Calif., Oct. 27, 2021 /PRNewswire/ -- \nHighlights from this announcement:\nDesignWare Interface IP for the most widely used protocols delivers the required high bandwidth and low latency for efficient data connectivity in compute-intensive designs on TSMC N4P process DesignWare Foundation IP offers high-speed, area-optimized and low-power embedded memories, logic libraries, GPIOs and TCAMs Broad IP portfolio on TSMC's N4P process complements Synopsys' certified digital and custom design solutions for the process, accelerating time to silicon success To facilitate chip innovation and enable designers to quickly achieve silicon success of complex high-performance computing (HPC) and mobile SoCs, Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with TSMC to develop a broad portfolio of Synopsys DesignWare® Interface and Foundation IP on the TSMC N4P process. The collaboration enables designers to access high-quality IP that aligns with their aggressive design and project schedule requirements on TSMC's most advanced process, while optimizing for performance, power, area, bandwidth and latency.\n\"We work closely with our Open Innovation Platform® (OIP) ecosystem partners to enable next-generation designs benefiting from the significant power and performance boost of our newest N4P process, which provides unique PPA balance to allow customers to continue to deliver leading HPC, mobile and other high performance products,\" said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. \"TSMC's long-term collaboration with Synopsys continues to deliver high-quality DesignWare IP on TSMC's most advanced processes, allowing designers to fully realize the advantages of the N4P process and launch differentiated products quickly to the market.\"\n\"Developing DesignWare IP on TSMC N4P process gives designers confidence that they can quickly integrate the IP into their designs and benefit from the performance, power and area improvements of the N4P process technology,\" said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. \"Our significant investment in developing silicon-proven and standards-compliant IP on the most advanced ...