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Synopsys Accelerates High-Performance Computing SoC Designs with Industry's Broadest IP Portfolio for TSMC's 5nm Process Technology
High-Quality DesignWare Interface and Foundation IP Deliver Leading Power, Performance and Area MOUNTAIN VIEW, Calif., May 11, 2020 /PRNewswire/ --
About this update from Synopsys, Inc.
[{"type":"text","content":"High-Quality DesignWare Interface and Foundation IP Deliver Leading Power, Performance and Area\n\n\nMOUNTAIN VIEW, Calif., May 11, 2020 /PRNewswire/ -- \nHighlights:\nDesignWare Interface PHY IP portfolio, including 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, CCIX, and Memory Interfaces, enables highest data rates High-Performance Memory Interface IP solution for DDR5, LPDDR5, and HBM2/2E delivers maximum memory bandwidth and power efficiency Die-to-Die PHYs for 112G USR/XSR connectivity and for High-Bandwidth Interconnect leveraging wide-parallel technology deliver reliable links with extremely low latency Optimized Foundation IP, such as logic libraries, multi-port memory compilers, and TCAMs, delivers maximum performance with low power consumptionSynopsys, Inc. (Nasdaq: SNPS) today announced the industry's broadest portfolio of high-quality IP on TSMC's 5nm process technology for high-performance computing system-on chips (SoCs). The DesignWare® IP portfolio on the TSMC process, encompassing interface IP for the most widely used high-speed protocols and foundation IP, accelerates development of SoCs for high-end cloud computing, AI accelerators, networking and storage applications. The combination of Synopsys' market-leading DesignWare IP and TSMC's 5nm process enables designers to achieve the aggressive performance, power, and density requirements of their designs, while lowering integration risk.\n\"Our long-term collaboration with Synopsys has resulted in delivering DesignWare IP on the most advanced TSMC processes, enabling our mutual customers to achieve many first-pass silicon successes in a wide range of markets including high-performance computing,\" said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. \"Synopsys' broad DesignWare IP portfolio on TSMC's advanced process technologies helps designers quickly incorporate the necessary functionality into their designs, while benefiting from the significant power and performance boost of our 5nm process technology, the most advanced foundry solution.\"\n\"For nearly two decades, Synopsys has been at the forefront of delivering high-quality DesignWare IP with unmatched power, performance, and area for every generation of TSMC's process technologies,\" said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. ...