Press release
Synopsys Accelerates Advanced Chip Design with First-Pass Silicon Success of IP Portfolio on TSMC 3nm Process
Industry's Broadest IP Portfolio on TSMC N3E Yields Exceptional Power, Performance and Area for AI, Mobile and HPC Highlights: Synopsys IP on TSMC N3E process
About this update from Synopsys, Inc.
[{"type":"text","content":"Industry's Broadest IP Portfolio on TSMC N3E Yields Exceptional Power, Performance and Area for AI, Mobile and HPC \nHighlights:\nSynopsys IP on TSMC N3E process delivers a competitive edge for chipmakers looking to reduce integration risk and accelerate time to first-pass silicon successStandards-compliant Synopsys Interface IP, including 112G Ethernet, LPDDR5X, DDR5, PCIe, USB/DisplayPort and MIPI C/D-PHY, enables wide interoperabilityBroad IP portfolio on TSMC's N3E process complements Synopsys' certified digital and custom design solutions to boost performance and minimize power consumptionSUNNYVALE, Calif., July 20, 2023 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) technology is unleashing a new wave of advanced designs with the industry's broadest portfolio of interface IP for the TSMC N3E process. Silicon success of Synopsys IP across multiple product lines, including the most widely used protocols, delivers leading power, performance, area (PPA) and latency. Synopsys' IP for the TSMC N3E node offers a fast path to TSMC N3P integration and enables chip designers to accelerate development of their AI, high-performance computing (HPC) and mobile designs. \n\"Synopsys provides a broad portfolio of high-quality IP that helps designers achieve their design goals and quickly integrate the necessary IP into their designs with less risk,\" said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. \"Synopsys IP for TSMC's 3nm process has been adopted by dozens of leading companies to accelerate their development time, quickly achieve silicon success and speed their time to market.\"\n\"Our longstanding collaboration with Synopsys enables our mutual customers to benefit from a broad portfolio of IP that has been proven on TSMC's advanced process technologies,\" said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. \"The silicon success of Synopsys IP on TSMC's N3E process underscores our collective efforts to help designers address the stringent PPA and latency requirements of their SoC designs and accelerate silicon innovation for the next-generation AI, HPC and mobile applications.\"\nAdditional Resources\nMinimize Design Risk and Achieve First-Pass Silicon Success on TSMC's N3E ProcessSynopsys Advances Designs on TSMC N3E Process with Production-Proven EDA Flows and B...