Press release
Microchip Teams Up with Intelligent Hardware Korea (IHWK) to Develop an Analog Compute Platform to Accelerate Edge AI/ML Inferencing
Using Microchip’s memBrain™ nonvolatile in-memory compute technology and working with universities, IHWK is creating a SoC processor for neurotechnology
About this update from Microchip Technology Incorporated
[{"type":"text","content":"Using Microchip’s memBrain™ nonvolatile in-memory compute technology and working with universities, IHWK is creating a SoC processor for neurotechnology devices\nCHANDLER, Ariz., Sept. 13, 2023 (GLOBE NEWSWIRE) -- To address the rapid rise of Artificial Intelligence (AI) computing at the edge of the network and its associated inferencing algorithms, Intelligent Hardware Korea (IHWK) is developing a neuromorphic computing platform for neurotechnology devices and field programmable neuromorphic devices. Microchip Technology (Nasdaq: MCHP), via its Silicon Storage Technology (SST) subsidiary, is assisting with development of this platform by providing an evaluation system for its SuperFlash® memBrain™ neuromorphic memory solution. The solution is based on Microchip’s industry-proven nonvolatile memory (NVM) SuperFlash technology and is optimized to perform vector matrix multiplication (VMM) for neural networks through an analog in-memory compute approach. The memBrain technology evaluation kit is designed to enable IHWK to demonstrate the absolute power efficiency of its neuromorphic computing platform for running inferencing algorithms at the edge. The end goal is to create an ultra-low-power analog processing unit (APU) for applications such as generative AI models, autonomous cars, medical diagnosis, voice processing, security/surveillance and commercial drones. As current neural net models for edge inference may require 50 million or more synapses (weights) for processing, it becomes challenging to have enough bandwidth for the off-chip DRAM required by purely digital solutions, creating a bottleneck for neural net computing that throttles overall compute power. In contrast, the memBrain solution both stores synaptic weights in the on-chip floating gate in ultra-low-power sub-threshold mode and uses the same memory cells to perform the computations—offering significant improvements in both power efficiency and system latency. When compared to traditional digital DSP and SRAM/DRAM based approaches, it delivers 10 to 20 times lower power usage per inference decision and can significantly reduce the overall bill of materials. To develop the APU, IHWK is also working with Korea Advanced Institute of Science & Technology (KAIST), Daejeon, for device development and Yonsei University, Seoul, for device design assistance. The final AP...