Press release
CEVA Unveils World's Most Powerful DSP Architecture
- Gen4 CEVA-XC architecture offers highest performance of 1,600 GOPS, innovative dynamic multithreading and advanced pipeline to reach operating speeds of
About this update from Ceva, Inc.
[{"type":"text","content":"- Gen4 CEVA-XC architecture offers highest performance of 1,600 GOPS, innovative dynamic multithreading and advanced pipeline to reach operating speeds of 1.8GHz at 7nm\n - CEVA-XC16, first processor based on the architecture, targets 5G Intelligent Radio Access Networks (RAN) and enterprise access points, with 2.5X improvement in peak performance\n\n\n\n \n \n MOUNTAIN VIEW, Calif., March 4, 2020 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading licensor of wireless connectivity and smart sensing technologies, today announced the unveiling of the world's most powerful DSP architecture, the Gen4 CEVA-XC. This new architecture delivers unmatched performance for the most complex parallel processing workloads required for 5G endpoints and Radio Access Networks (RAN), enterprise access points and other multigigabit low latency applications.\nThe Gen4 CEVA-XC unifies the principles of scalar and vector processing in a powerful architecture, enabling two-times 8-way VLIW and up to an unprecedented 14,000 bits of data level parallelism. It incorporates an advanced, deep pipeline architecture enabling operating speeds of 1.8 GHz at a 7nm process node using a unique physical design architecture for a fully synthesizable design flow, and an innovative multithreading design. This allows the processors to be dynamically reconfigured as either a wide SIMD machine or divided into smaller simultaneous SIMD threads. The Gen4 CEVA-XC architecture also features a novel memory subsystem, using 2048-bit memory bandwidth, with coherent, tightly-coupled memory to support efficient simultaneous multithreading and memory access.\nMike Demler, Senior Analyst at The Linley Group, commented: \"The Gen4 CEVA-XC architecture demonstrates CEVA's industry-leading commitment to driving DSP innovation forward for parallel processing. Its dynamically reconfigurable multithreading and high speed design, along with comprehensive capabilities for both control and arithmetic processing, sets the foundation for the proliferation of ASICs and ASSPs for 5G infrastructure and endpoints.\"\nThe first processor based on the Gen4 CEVA-XC architecture is the multicore CEVA-XC16, the fastest DSP ever made. It is targeted for the rapid deployment of different form factors of 5G RAN architectures including Open RAN (O-RAN), Baseband Unit (BBU) aggregation as well as Wi-Fi...