Press release
DB GlobalChip Deploys Cadence’s Spectre FX and AMS Designer, Accelerating IP Verification by 2X
Cadence Spectre Technology enables DB GlobalChip to accelerate analog and mixed-signal IP development SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nCadence Spectre Technology enables DB GlobalChip to accelerate analog and mixed-signal IP development\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that DB GlobalChip has deployed the Cadence® Spectre® FX Simulator, integrated with Spectre AMS Designer, to verify its crucial analog and mixed-signal IP, achieving a 2X improvement in performance with the required accuracy compared to their incumbent flow. The Cadence solution allowed DB GlobalChip to speed its IP development and verification cycles, accelerating time to market.\n\n\nMeeting stringent design requirements for analog and mixed-signal IP while meeting customers’ timelines is a growing challenge. DB GlobalChip is continuously innovating its design methodologies to shorten design and verification cycles while meeting the desired accuracy of the results. DB GlobalChip successfully utilized the Spectre FX Simulator for its analog transistor-level designs and deployed the comprehensive mixed-signal simulation solution, Spectre AMS Designer, integrated with Spectre FX Simulator, to include digital control logic to account for analog/digital interaction effects with faster performance. The design team at DB GlobalChip leveraged the Cadence mixed-signal simulation solution’s out-of-the-box intuitive use model and comprehensive methodology support, which incorporates the Cadence Virtuoso® ADE Suite, providing comprehensive verification quality and coverage with significantly faster turnaround times to deliver IP to customers.\n\n\nDB GlobalChip leveraged the Spectre FX Simulator's multicore architecture to parallelize simulations and easy-to-use preset options for accuracy performance tuning in their mixed-signal and transistor-level simulations. This allowed their design and verification teams to improve simulation turnaround time by utilizing available hardware resources without trading off accuracy.\n\n\n“Complex analog and mixed-signal IP require very accurate FastSPICE simulations and a tight integration with the mixed-signal verification environment,” said Jeongtae Park, vice president at DB GlobalChip. “Our IP designers leveraged the intuitive use model and performance of Cadence’s comprehensive mixed-signal simulation solution and realized a 2X improvement in runtime and productivity while meeting stringent acc...