Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre‑Silicon Hardware Debug and Software Validation

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[{"type":"text","content":"\nHighlights:\n\n\nNew dynamic duo delivers 2X capacity and 1.5X higher performance compared to previous-generation Palladium Z1 and Protium X1 systems\n\n\nPalladium Z2 emulation based on a new custom emulation processor offers fastest, most predictable compiles and most comprehensive pre-silicon hardware debug capabilities\n\n\nProtium X2 prototyping based on latest Xilinx UltraScale+ VU19P FPGAs offers highest performance and fastest bring-up times for pre-silicon software validation of billion-gate designs\n\n\nCadence provides the most comprehensive solution for IP and SoC verification, hardware and software regressions, and early software development\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence® Palladium® Z2 Enterprise Emulation and Protium™ X2 Enterprise Prototyping systems to handle the exponentially increasing system design complexity and time-to-market pressures. Building upon Cadence’s current industry-leading Palladium Z1 emulation and Protium X1 prototyping platforms, these next-generation systems enable the highest throughput pre-silicon hardware debug and pre-silicon software validation for the industry’s largest multi-billion-gate system-on-chip (SoC) designs. Dubbed the Cadence “dynamic duo” for its tight integration with unified compiler and interfaces, the next-generation emulation processors and Xilinx UltraScale+ VU19P FPGAs in these systems provide customers with 2X capacity and 1.5X performance improvements over their predecessors, allowing Cadence customers to run more validation cycles on bigger chips in less time. Additionally, both systems offer breakthrough modular compile technology capable of compiling 10 billion gates in under 10 hours on the Palladium Z2 system and in under 24 hours on the Protium X2 system.\nThis press release features multimedia. View the full release here: https://www.businesswire.com/news/home/20210405005185/en/The Next-Generation Cadence Palladium Z2 and Protium X2 Systems to Accelerate Pre-Silicon Hardware Debug and Software Validation (Photo: Business Wire)\n“The complexity of our high-end graphics and hyperscale designs increases with each generation, while our time-to-market schedules tighten,” said Narendra Konda, senior director, hardware engineering at NVIDIA Corporation. “Using the common front-end...

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