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Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design

Highlights Cadence Tempus Timing Solution and Quantus Extraction Solution enabled Samsung Foundry to confidently sign off their SF5A design while achieving

articleCadence Design Systems, Inc.November 30, 20235/company/cadence-design-systems-inc/news/cadence-signoff-solutions-empower-samsung-foundrys-breakthrough-success-on-5g
Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design

About this update from Cadence Design Systems, Inc.

[{"type":"text","content":"\nHighlights\n\n\n\nCadence Tempus Timing Solution and Quantus Extraction Solution enabled Samsung Foundry to confidently sign off their SF5A design while achieving optimal PPA results\n\n\n\nAs a result of their first deployment of Cadence signoff solutions, Samsung Foundry realized a 2X productivity boost for faster design closure\n\n\n\n \n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.\n\n\nOne of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.\n\n\n“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics, Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”\n\n\n“The ...

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