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Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow
Highlights: Cadence and TSMC collaborate on N6RF design enablement to accelerate innovation in mobile, 5G and wireless applications Joint customers are
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\nCadence and TSMC collaborate on N6RF design enablement to accelerate innovation in mobile, 5G and wireless applications\n\n\nJoint customers are designing with the new PDK based on the N6RF design flow\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Cadence® RFIC solutions are enabled to support TSMC’s N6RF Design Reference Flow and process design kit (PDK) to accelerate mobile, 5G and wireless innovation. Through the ongoing collaboration between Cadence and TSMC, mutual customers are already designing with the Cadence solutions for TSMC’s latest N6RF CMOS semiconductor technology.\n\nThe Cadence RFIC solutions support the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence. To learn more about Cadence RFIC solutions, visit www.cadence.com/go/rfrfic.\n\nOptimized for TSMC’s N6RF process technology, the Cadence Virtuoso® Schematic Editor, Virtuoso ADE Suite and the integrated Spectre® X Simulator and RF option are included in the RF Design Reference Flow. Customers can benefit from several key features, which enable them to effectively manage corner simulations, perform statistical analyses and achieve design centering and circuit optimization. Additionally, the flows offer seamless integration between the Cadence EMX® Planar 3D Solver and the Virtuoso Layout Suite EXL implementation environment, which enables designers to streamline EM modeling tasks and leverage automation to stitch S-parameter models into the golden design schematic for RF simulations automatically.\n\nFor post-layout analysis, the S-parameter models are layered into Cadence Quantus™ Extraction Solution results for high-fidelity RF signoff circuit and EM-IR simulations. Overall, the new Cadence RFIC full flow offers an efficient methodology that lets engineers achieve design goals—performance, power efficiency and reliability—in a single, tightly integrated design environment.\n\n“Through our ongoing collaboration with Cadence, we’re making it easier for customers to achieve their productivity goals using the jointly developed design flow and our advanced N6RF process technology, which offers significant performance and power efficiency boosts,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “With the ...