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Cadence Integrity 3D-IC Platform Supports TSMC 3DFabric™ Technologies for Advanced Multi-Chiplet Designs
Highlights: The Cadence 3D-IC solution centers on the Integrity 3D-IC platform, which provides integrated planning, implementation and system analysis to
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\nThe Cadence 3D-IC solution centers on the Integrity 3D-IC platform, which provides integrated planning, implementation and system analysis to optimize PPA for multi-chiplet systems\n\n\nThe Tempus Timing Signoff Solution with inter-die analysis and STA technologies results in faster time to tapeout\n\n\nThe Voltus IC Power Integrity Solution, tightly coupled with the Celsius Thermal Solver, facilitates multi-die IR drop and thermal analysis for design robustness\n\n\nCustomers can confidently adopt the Cadence 3D-IC solution and TSMC 3DFabric technologies to create next-generation hyperscale computing, mobile and automotive applications\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it is working with TSMC to accelerate 3D-IC multi-chiplet design innovation. As part of the collaboration, the Cadence® Integrity™ 3D-IC platform, the industry’s first unified platform for 3D-IC planning, implementation and system analysis, is enabled for TSMC 3DFabric™ technologies, TSMC’s comprehensive family of 3D silicon stacking and advanced packaging technologies. In addition, the Cadence Tempus™ Timing Signoff Solution has been enhanced to support a new stacking static timing analysis (STA) signoff methodology, shortening design turnaround time. Through these latest milestones, customers can confidently adopt the Cadence 3D-IC solution and TSMC’s 3DFabric technologies to create competitive hyperscale computing, mobile and automotive applications.\n\nThe Cadence 3D-IC solution supports TSMC’s full set of 3D silicon stacking and advanced packaging technologies, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC™). The 3D-IC solution also aligns with the Cadence Intelligent System Design™ strategy, driving system-on-chip (SoC) design excellence.\n\nThe Cadence Integrity 3D-IC platform provides 3D chip and package planning, implementation and system analysis in a single, unified cockpit. This lets customers streamline multi-chiplet design planning, implementation and analysis of 3D silicon stacking while also optimizing engineering productivity, power, performance and area (PPA). Also, the platform has co-design capabilities integrated with the Cadence Allegro® packaging technologies and the Cadence Virtuo...