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Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack
Highlights: Integrity 3D-IC is Cadence’s next-generation multi-chip design solution, integrating silicon and package planning and implementation with system
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\nIntegrity 3D-IC is Cadence’s next-generation multi-chip design solution, integrating silicon and package planning and implementation with system analysis and signoff to enable system-driven PPA optimization\n\n\nNative 3D partitioning flow automates intelligent creation of memory-on-logic 3D stacking configuration, providing PPA improvements for 3D stack designs\n\n\nCustomers can confidently adopt the Cadence Integrity 3D-IC platform and Samsung Foundry’s multi-die implementation flow to create next-generation hyperscale computing, mobile, automotive and AI applications\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS), a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE™), today announced that Samsung Foundry has qualified the Cadence® Integrity™ 3D-IC platform’s 2D-to-3D native 3D partitioning flow. Using the new flow, customers can partition existing 2D designs into 3D memory-on-logic configurations and achieve better power, performance and area (PPA) with a homogeneous 3D stack when compared with the original 2D design. The flow also provides robust 3D-IC system planning, implementation and early analysis capabilities for the partitioned design, which is ideal for customers creating complex, next-generation hyperscale computing, mobile, automotive and AI applications.\n\nHitting a memory wall where RAM access cannot keep pace with CPU execution speed causes the overall system to slow down due to memory latency. One way to overcome this is to place memories on top of the logic in a homogenous stacking configuration. The configuration, when mounted on the same package, reduces wirelength and area and speeds up memory access, thus helping to improve the performance of the CPU core.\n\nThe Integrity 3D-IC platform’s 3D partitioning enables the user to separate out memory macros and standard cells and place them on two different dies within a 3D homogeneous stack. The automated flow performs partitioning and full implementation of the 3D stack while building connections between the macros and standard cells. Once the contents of each die are finalized, the system and package can be implemented in the Integrity 3D-IC platform, enabling bump planning, implementation, co-design with other dies, and early analysis of thermal, power and static timing analysis...