Press release
Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity
Cadence Janus NoC enables design teams to achieve better PPA faster and with lower risk, freeing up valuable engineering resources for SoC differentiation
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nCadence Janus NoC enables design teams to achieve better PPA faster and with lower risk, freeing up valuable engineering resources for SoC differentiation\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today expanded its system IP portfolio with the addition of the Cadence® Janus™ Network-on-Chip (NoC). As larger, more complex SoCs and disaggregated multi-chip systems proliferate to accommodate today’s escalating compute demands, data delivery within and between silicon components has become increasingly challenging—impacting power, performance and area (PPA). The Cadence Janus NoC manages these simultaneous high-speed communications efficiently with minimal latency, enabling customers to achieve their PPA targets faster and with lower risk.\n\nThis press release features multimedia. View the full release here: https://www.businesswire.com/news/home/20240625350157/en/The Cadence Janus Network-on-Chip (NoC) efficiently manages simultaneous high-speed communications within and between silicon components with minimal latency. This enables customers to achieve their power, performance and area (PPA) targets faster and with lower risk, freeing up valuable engineering resources for SoC differentiation. (Graphic: Business Wire)\n“Cadence is an established leader in IP and design quality, and we continue to invest in our foundational interface and processor IP, system IP, software and design services capabilities to enable our customers to develop differentiated and disaggregated designs,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “The addition of the Cadence Janus NoC to our growing system IP portfolio is a key milestone in this strategy. Our evolution from an IP provider to an SoC design partner delivers greater value to our customers, empowering them to focus valuable engineering resources on differentiating their silicon.”\n\n\nThe Cadence Janus NoC leverages Cadence’s legacy of trusted and time-proven Tensilica® RTL generation tools. Customers can utilize Cadence’s extensive portfolio of software and hardware for simulation and emulation of their NoC and gain deep insights into its performance using Cadence’s System Performance Analysis tool (SPA). By enabling architectural exploration, this flow results in the best NoC design to ...