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Cadence Expands Design IP Portfolio with 56G Long-Reach PAM4 SerDes on TSMC N7 and N6 Processes
DSP-based, multi-rate SerDes IP is optimized for power, performance and area for next-generation 5G and AI/ML SoC design SAN JOSE, Calif.--(BUSINESS WIRE)--
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nDSP-based, multi-rate SerDes IP is optimized for power, performance and area for next-generation 5G and AI/ML SoC design\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies. Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data center and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. To address this broader market, Cadence has expanded its PAM4 SerDes portfolio with 56G long-reach SerDes IP on the TSMC N7 and N6 processes delivering optimized power, performance and area (PPA). For more information on the 56G long-reach PAM4 SerDes, please visit www.cadence.com/go/56GSerDes.\n\n\nCadence is ready to engage with customers immediately on 5G, compute server processor and machine learning workload-accelerator system-on-chip (SoC) design enablement. The Cadence® 56G long-reach SerDes IP delivers design excellence in support of the Cadence Intelligent System Design™ strategy, offering designers a number of benefits, including:\n\n\n\nBest-in-class 36db+ insertion loss using Cadence’s well-proven multi-rate DSP technology\n\n\nIndustrial temperature range, CPRI data rate support and per-lane PLL are ideal for 5G applications\n\n\n56G long-reach performance has been achieved on N7 test silicon and is compatible with the N6 process\n\n\nFully compliant with the IEEE standard specification\n\n\nProgrammable power configurations via a unique firmware-controlled adaptive power optimizer, which provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements\n\n\nOptimal data recovery through the programmable DSP-based architecture, which allows optimal power delivery for a given reach and provides superior data recovery under lossy and noisy channel conditions\n\n\nImproved flexibility enabled by the extended reach capability lets customers use lower cost PCBs and achieve greater flexibility in PCB and system design\n\n\n\n“We are pleased to see Cadence expand its PAM4 offerings to include 56G and extend support to TSMC N7 and N6 process technologies,” said Suk Lee, senior direc...