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Cadence Digital and Custom/Analog Flows Achieve the Latest TSMC N3 and N4 Certifications
Highlights: Companies collaborate on design enablement for TSMC N3 and N4 processes to accelerate mobile, AI and hyperscale computing innovation Joint
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\nCompanies collaborate on design enablement for TSMC N3 and N4 processes to accelerate mobile, AI and hyperscale computing innovation\n\n\nJoint customers actively designing with new PDKs based on the certified N3 and N4 flows\n\n\nComplete, integrated RTL-to-GDS flow enabled for the TSMC N3 and N4 process technologies, providing optimal PPA\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital and custom/analog flows have achieved certification for TSMC’s N3 and N4 process technologies in support of the latest Design Rule Manual (DRM). Through continued collaborations, Cadence and TSMC delivered the corresponding process design kits (PDKs) for TSMC N3 and N4 processes to accelerate mobile, AI and hyperscale computing innovation. In addition, mutual customers have already validated the benefits of the Cadence® flows and TSMC’s process technologies through successful tapeouts.\n\nTo learn more about the Cadence digital and custom/analog advanced-node solutions, which support the Cadence Intelligent System Design™ strategy and enable system-on-chip (SoC) design excellence, visit www.cadence.com/go/advndtsmc34.\n\nN3 and N4 Digital Flow Certifications\n\nCadence worked closely with TSMC to optimize the digital flow for TSMC’s advanced N3 and N4 process technologies to help customers achieve power, performance and area (PPA) goals and speed time to market. The complete, integrated RTL-to-GDS flow includes the Cadence Innovus™ Implementation System, Liberate™ Characterization Solution, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Signoff Solution and ECO Option, and the Voltus™ IC Power Integrity Solution. Additionally, the Cadence Genus™ Synthesis Solution and predictive iSpatial technology are enabled for the N3 and N4 process technologies.\n\nThe digital full flow enables customers to successfully design on TSMC’s N3 and N4 process technologies through several capabilities, including:\n\n\nEfficient processing of large libraries: Among the variations of threshold voltage and drive strength, the Cadence flow efficiently processes these large libraries, ensuring the best run-time for increasingly complex designs.\n\n\nTiming analysis accuracy: N3 requires additional accuracy during library cell characterization and static timing...