Press release
Cadence Delivers 13 New VIP and Expands System VIP Portfolio to Accelerate Automotive, Hyperscale Data Center and Mobile SoC Verification
New additions enable fast and comprehensive verification, ensuring SoCs meet the latest standard specifications SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nNew additions enable fast and comprehensive verification, ensuring SoCs meet the latest standard specifications\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of 13 new Verification IP (VIP) solutions that enable engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols. The new Cadence® VIP offerings empower customers to confidently develop their next-generation automotive, hyperscale data center and mobile SoCs and microcontrollers while keeping pace with the latest industry standards, including Arm® AMBA® 5 CHI-f, Universal Chiplet Interconnect Express™ (UCIe™), GDDR7, DDR5 DIMM, MIPI® A-PHY® and SoundWire® I3S, and USB4 2.0 interfaces.\n\nThe new Cadence VIP offer customers a comprehensive verification solution for the most complex protocols. Cadence customers have access to a consistent application programming interface (API) across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP support multiple application areas and specifications, including:\n\n\nHyperscale data center:\n\n\nUCIe\n\n\nAMBA 5 CHI-f\n\n\nDTI\n\n\nLatest version of DDR5 DIMM\n\n\n\n\nAutomotive:\n\n\nMIPI A-PHY 1.1\n\n\nCAN XL\n\n\nFlash ONFI 5.1\n\n\n\n\nConsumer and mobile:\n\n\nUSB4 2.0\n\n\nGDDR7\n\n\nMIPI SoundWire I3S (SWI3S)\n\n\nLatest version of LPDDR\n\n\nDFI\n\n\nHDMI 2.1\n\n\n\n\nAll Cadence VIP solutions include Cadence TripleCheck™ technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The new VIP also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers. Using the expanded System VIP portfolio, customers can experience up to 10X efficiency improvements compared to a manual process for SoC verification.\n\n“The Cadence memory VIP is a critical part of our verification process and instrumental in the successful deployment of our memory PHY IP,” said Ricky Lau, co-founder and CTO of The Six Semiconductor Inc. “Cadence continues to deliver new VIP offerings and advanced SoC ...