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Cadence Collaborates With Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm
Highlights: Cadence 20.1 digital full flow tuned for Samsung Foundry advanced-process nodes, enabling optimal PPA and first-pass silicon success HPC
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\nCadence 20.1 digital full flow tuned for Samsung Foundry advanced-process nodes, enabling optimal PPA and first-pass silicon success\n\n\nHPC reference flows based on iSpatial technology enable rapid design implementation\n\n\nDigital flow’s ML and concurrent macro, standard cell and placement capabilities deliver improved productivity and design optimization\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has optimized the Cadence® digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm. Through the collaboration, designers can use the Cadence tools to achieve optimal power, performance, and area (PPA) and deliver accurate, first-pass silicon for hyperscale computing applications.\n\nThe Cadence digital 20.1 flow provides capabilities that are well-suited for Samsung Foundry’s advanced-process technologies. For example, the iSpatial technology allows a seamless transition from the Genus™ Synthesis Solution to the Innovus™ Implementation System using a common user interface and database. Machine learning (ML) capabilities enable users to leverage their existing designs to train the GigaOpt™ optimization technology to minimize design margins versus traditional place-and-route flows.\n\nCombined with a high-performance clock mesh architecture, the digital GigaPlace XL technology offers concurrent macro and standard cell placement that enables automated floorplanning, delivering better designer productivity and significantly improved wirelength and power. Unified implementation, timing and IR signoff engines enhance signoff convergence and reduce design margins and iterations. To speed the design process in Samsung Foundry’s advanced-process technologies, example flows are now provided for common high-performance computing (HPC) tasks such as concurrent macro and standard cell placement, clock mesh, balanced H Tree clock distribution, power delivery network and IR optimization.\n\nThe complete Cadence RTL-to-GDS flow optimized for Samsung Foundry process technologies includes the Genus Synthesis Solution, Cadence Modus DFT Software Solution, Innovus Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Tempus ECO Option, Tempus Power Integrity Solution, Voltus™ IC Power Integrity Solution,...