Press release
Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows
Highlights: Cadence optimized its AI-driven RTL-to-GDS digital flow and delivered corresponding 5nm and 3nm RAKs for the Arm Neoverse V2 platform, enabling
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\n\nCadence optimized its AI-driven RTL-to-GDS digital flow and delivered corresponding 5nm and 3nm RAKs for the Arm Neoverse V2 platform, enabling designers to get to market faster\n\n\n\nCadence AI-driven verification full flow provides Neoverse V2 platform designers with optimal verification throughput and preparedness for Arm SystemReady compliance\n\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced an expanded collaboration with Arm to speed data center silicon success on the Arm® Neoverse™ V2 platform. Through the collaboration, Cadence fine-tuned its AI-driven RTL-to-GDS digital flow for Neoverse V2 and delivered corresponding 5nm and 3nm Rapid Adoption Kits (RAKs), empowering customers to achieve power, performance and area (PPA) targets faster. In addition, the Cadence® AI-driven verification full flow supports Neoverse V2, providing designers with optimal verification throughput and preparedness for Arm SystemReady compliance.\n\n\nCadence AI-Driven Digital Full Flow for the Neoverse V2 Platform\n\n\nThe comprehensive AI-driven Cadence RTL-to-GDS digital full flow RAKs for 3nm and 5nm nodes includes the Genus™ Synthesis Solution, Modus DFT Software Solution, Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Solution and ECO Option, Voltus™ IC Power Integrity Solution, Conformal® Equivalence Checking, Conformal Low Power and the AI-based Cadence Cerebrus™ Intelligent Chip Explorer.\n\n\nThe digital RAKs provide Arm Neoverse V2 designers with several key benefits. For example, the Cadence Cerebrus AI capabilities automate and scale digital chip design, delivering better PPA and improving designer productivity. Cadence iSpatial technology provides an integrated and predictable implementation flow for the faster design closure. The RAKs also include a smart hierarchy flow that delivers optimal turnaround times on large, high-performance CPUs. The Tempus ECO technology offers signoff-accurate final design closure based on path-based analysis. Finally, the RAKs incorporate the GigaOpt activity-aware power optimization engine to significantly reduce dynamic power consumption.\n\n\nCadence AI-Driven Verification Full Flow Support for Arm Neoverse V2\n\n\nThe Cadence AI-driven verification full flow optimized to support Arm Neoverse...