Press release
Cadence AI-Powered Virtuoso Studio Supports RF and mmWave Design Reference Flows for TSMC N16RF, N6RF and N4PRF
Highlights: Cadence’s comprehensive, optimized RF flow now includes the new, AI-powered Virtuoso Studio to support TSMC’s N16 mmWave, N6RF and N4PRF design
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\n\nCadence’s comprehensive, optimized RF flow now includes the new, AI-powered Virtuoso Studio to support TSMC’s N16 mmWave, N6RF and N4PRF design reference flows\n\n\n\nJoint customers are actively designing with TSMC PDKs\n\n\n\nCadence and TSMC’s latest collaboration accelerates innovation in mobile, 5G, and WiFi-7 wireless applications\n\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced it has collaborated with TSMC to integrate the new Cadence® Virtuoso® Studio into the TSMC N16 mmWave design reference flow and N6RF design reference flow, and added support for the N4PRF design reference flow. With this latest development in Cadence’s and TSMC’s long history of collaboration, joint customers now have access to complete RF design reference flows on the N16, N6, and N4PRF processes for developing optimized, highly reliable, next-generation RFIC designs for use in radar, 5G and WiFi-7 wireless applications for the mobile, automotive, healthcare and aerospace markets. Mutual customers are already using the design reference flows and corresponding TSMC process design kits (PDKs) for RFIC design projects.\n\n\nThe Cadence RFIC solution supports TSMC’s advanced processes and features automation capabilities to help customers spend less time developing and integrating critical RF functionality into their designs. The solution supports all aspects of RF design, including passive device modeling, assisted layout automation, and electromagnetics (EM) simulations.\n\n\nThe flows are supported by the latest version of the Cadence Virtuoso Schematic Editor and can deliver unmatched productivity benefits. Additionally, the flows enable a seamless integration between the Cadence EMX® Planar 3D Solver and Quantus™ Smart View tools for full-circuit extraction without parasitic double counting. The flows are newly enhanced to use purpose mapping for intelligent device scaling when migrating schematics between technology nodes. Purpose mapping allows designers to capture the purpose of devices so that they may be scaled correctly upon process migration, according to their function in the circuit. Furthermore, a new advanced results reviewer provides valuable insight into design sensitivities such as managing corner simulations, and achieving design centering and circuit opti...