Press release
Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP
Highlights: Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on
About this update from Cadence Design Systems, Inc.
[{"type":"text","content":"\nHighlights:\n\n\n\nProven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process\n\n\n\n224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon success\n\n\n\n112G-ELR SerDes silicon results on the TSMC N3E process showing optimal PPA\n\n\n\nMultiple Cadence IP test chips have successfully taped out on the TSMC N3E process, including PCIe 6.0 and 5.0, 64G-LR Multi-Protocol PHY, LPDDR5x/5, GDDR7/6 and UCIe\n\n\n\n SAN JOSE, Calif.--(BUSINESS WIRE)--\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced it has expanded its design IP portfolio on TSMC’s 3nm (N3E) process—most notably with the addition of the flagship Cadence® 224G Long-Reach (224G-LR) SerDes PHY IP, which has achieved first-pass silicon success. Other Cadence Design IP on the advanced TSMC N3E process has demonstrated silicon success or taped out, providing mutual customers with a wide range of high-speed interface and memory IP for their most advanced designs. Cadence’s broad portfolio on TSMC’s N3E process delivers industry-leading power, performance and area (PPA) to target the most demanding networking, hyperscale computing, artificial intelligence and machine learning (AI/ML), chiplet, automotive and storage applications.\n\n\nWith the proliferation of bandwidth-hungry, low-latency applications fueled by generative AI and large language models (LLMs), the need for innovative IP solutions that enable efficient and robust high-speed data transmission has become paramount. Addressing this surging demand, the new 224G-LR SerDes PHY IP and other leading Cadence interface IP on the TSMC N3E process usher in a new era of innovation and high-speed connectivity. The 224G-LR SerDes PHY IP features an innovative architecture providing an exceptional combination of speed, reach and power efficiency. Key features include:\n\n\n\nSupport for full-duplex 1-225Gbps data rates with excellent LR performance\n\n\n\nOptimized power efficiency configurable for different channel reaches (LR, MR, VSR)\n\n\n\nBuilt-in intelligence to enhance reliability and system robustness\n\n\n\nThe 224G-LR PHY IP is part of the Cadence IP portfolio on TSMC’s advanced N3E process, which also includes 112G LR SerDes PHY IP, PCI Express® (PCIe®) 6.0/5.0/4.0/3.0/2.0, 64G/32G Multi-Protocol SerDes, Universal Chip...