Press release

Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs

Highlights: - Productive: Designed for maximum engineering productivity and time-to-market acceleration for connecting semiconductor IP blocks and sub-systems

articleArteris, Inc.March 13, 20244/company/arteris-inc/news/arteris-expands-ncore-cache-coherent-interconnect-ip-to-accelerate-leading-edge
Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs

About this update from Arteris, Inc.

[{"type":"text","content":"Highlights: - Productive: Designed for maximum engineering productivity and time-to-market acceleration for connecting semiconductor IP blocks and sub-systems for Arm and RISC-V-based designs, accelerating time to results.- Configurable: Scales across a mix of fully coherent, IO-coherent, non-coherent, memory and peripheral interfaces using a variety of NoC topologies, delivering best-in-class architectural flexibility.- Functionally Safe: Ready to meet ISO 26262 requirements from ASIL B to ASIL D for automotive and other mission critical systems. CAMPBELL, Calif., March 13, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced the immediate availability of the latest release of Ncore cache coherent network-on-chip (NoC) IP. Ncore ensures low latency integration of hardware accelerators into a coherent domain, enabling the speed and efficiency required for cutting-edge applications in complex SoC designs. Deploying Ncore can save SoC design teams upwards of 50 years of engineering effort per project compared to manually generated interconnect solutions. The latest release of Ncore works with multiple processor IPs, including RISC-V and the next-generation Armv9 Cortex processor IP. Ncore boasts multi-protocol support, allowing seamless integration of IPs connected to the same NoC fabric. Designers can choose from CHI-E, CHI-B and ACE fully coherent agent interfaces and ACE-Lite IO-coherent interfaces. AXI is also supported for interfacing with sub-systems or devices without coherency requirements. These capabilities enhance the flexibility and adaptability of Ncore, making it an ideal solution for complex and evolving SoC designs, including safety-critical applications. \"We have worked with Arteris network-on-chip technology since 2010, using it in our advanced autonomous driving and driver-assistance technologies,” said Leonid Smolyansky, Ph.D.SVP SoC Architecture, Security & Safety at Mobileye. “We are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerance and reliable SoC design.” With configurability and scalability at its core, Ncore empowers SoC designers to meet specific power, performance and area requirements with the flexible fine-tuning of the NoC architecture. N...

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